TWR-P1025 Freescale Semiconductor, TWR-P1025 Datasheet - Page 22

• Manufacturer Part Number: TWR-P1025
• Description: Development Boards & Kits - Other Processors TOWER MODULE P1025
• Manufacturer: Freescale Semiconductor

Specifications of TWR-P1025

• Rohs: yes
• Product: Development Platforms
• Tool Is For Evaluation Of: P1025
• Core: PowerPC e500
• Interface Type: I2C, UART, USB 2.0
• Operating Supply Voltage: 5 V
• For Use With: Freescale Tower System

The codewarrior initialization for the DDR3 controller are:
Freescale Semiconductor
Signal Group
# DDR Controllers Setup
# DDR_SDRAM_CFG
reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG = 0x470C0000
#CS0_BNDS
reg ${DDR_CONT_GROUP}CS0_BNDS = 0x0000001f
#CS1_BNDS
reg ${DDR_CONT_GROUP}CS1_BNDS = 0x00000000
#CS0_CNFG
reg ${DDR_CONT_GROUP}CS0_CONFIG = 0x80014202
#CS1_CNFG
reg ${DDR_CONT_GROUP}CS1_CONFIG = 0x00000000
# TIMING_CFG_0
#reg ${DDR_CONT_GROUP}TIMING_CFG_0 = 0x00330004
reg ${DDR_CONT_GROUP}TIMING_CFG_0 = 0x00220004
# TIMING_CFG_1
#reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x6f6b4846
reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x5c5b6544
# TIMING_CFG_2
#reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa8c8cf
reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa880de
# TIMING_CFG_3
#reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000
reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000
# DDR_SDRAM_CFG_2
#reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401040
reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401050
Clocks
Misc
P1 Signal
MCK0+/-
MCK1+/-
MDIC0
MDIC1
ZQ
TWR-P1025 Hardware User Guide, Rev. 2
Table 3-9. DDR3 Signals (continued)
DDR3 Device 1
MCK0+/-
RESET
Signal
NC
DDR3 Device 2
MCK0+/-
RESET
Signal
NC
mode 40ohm to
mode 40ohm to
Termination/
VSSQ (GND)
Half Strength
Half Strength
1.5V Tolerant
240 Ohm to
GVDD
Notes
GND
Driver calibration
Driver calibration
Clock/compleme
Hardware Description
ZQ calibration
Device Reset
Description
nt
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