AT28HC64BF-12JU Atmel, AT28HC64BF-12JU Datasheet - Page 3

• Manufacturer Part Number: AT28HC64BF-12JU
• Description: IC EEPROM 64KBIT 120NS 32PLCC
• Manufacturer: Atmel

Specifications of AT28HC64BF-12JU

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-PLCC
• Density: 64Kb
• Interface Type: Parallel
• Organization: 8Kx8
• Access Time (max): 120ns
• Write Protection: Yes
• Data Retention: 10Year
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Supply Current: 40mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Block Diagram
4. Device Operation
4.1
4.2
4.3
4.4
3648B–PEEPR–4/09
Read
Byte Write
Page Write
DATA Polling
The AT28HC64BF is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high-impedance state when either CE or OE is high. This dual line
control gives designers flexibility in preventing bus contention in their systems.
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of t
The page write operation of the AT28HC64BF allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 µs (t
If the t
internal programming operation. All bytes during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition during
the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
The AT28HC64BF features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during
the write cycle.
BLC
limit is exceeded, the AT28HC64BF will cease accepting data and commence the
WC
, a read operation will effectively be a polling operation.
ADDRESS
INPUTS
GND
VCC
WE
OE
CE
OE, CE and WE
X DECODER
Y DECODER
LOGIC
DATA INPUTS/OUTPUTS
INPUT/OUTPUT
IDENTIFICATION
CELL MATRIX
DATA LATCH
I/O0 - I/O7
BUFFERS
Y-GATING
BLC
) of the previous byte.
3