AT25DF641-S3H-B Atmel, AT25DF641-S3H-B Datasheet - Page 36

• Manufacturer Part Number: AT25DF641-S3H-B
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Memory Configuration: 32K Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.2. EPE Bit
10.1.3. WPP Bit
10.1.4. SWP Bits
10.1.5. WEL Bit
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The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one
byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the
logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an
attempt to erase or program a protected region or a locked down sector, an attempt to erase or program a
suspended sector, or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated
after every erase and program operation.
The WPP bit can be read to determine if the
The SWP bits provide feedback on the software protection status for the device. There are three possible
combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using
the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have
been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection
Registers command to determine which sectors are in fact protected.
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”
state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register commands.
The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition, the WEL bit
will be reset to the logical “0” state automatically under the following conditions:
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an
incomplete or unrecognized opcode being clocked into the device before the
WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase,
Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security
Register, or Write Status Register command must have been clocked into the device.
Atmel AT25DF641
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Sector Lockdown operation completes successfully or aborts
• Freeze Sector Lockdown State operation completes successfully or aborts
• Program OTP Security Register operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
WP
pin has been asserted or not.
CS
pin is deasserted. In order for the
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