AT24C512B-TH-T Atmel, AT24C512B-TH-T Datasheet - Page 6
![IC EEPROM 512KBIT 1MHZ 8TSSOP](/photos/6/83/68331/453-8-tssop_sml.jpg)
AT24C512B-TH-T
Manufacturer Part Number
AT24C512B-TH-T
Description
IC EEPROM 512KBIT 1MHZ 8TSSOP
Manufacturer
Atmel
Datasheet
1.AT24C512BN-SH25-T.pdf
(26 pages)
Specifications of AT24C512B-TH-T
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT24C512B-TH-T
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
AT24C512B-TH-T
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
3. Device Operation
Figure 3-1.
6
SCL
SDA
AT24C512B
Protocol Reset Condition
Start bit
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
ure 3-5 on page
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a)
upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b)
clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps have been completed.
1
2
8).
Dummy Clock Cycles
3
Figure 3-5 on page
8
9
8).
Start bit
Figure 3-4 on page
5297A–SEEPR–1/08
Stop bit
Fig-
8).