93C86-E/SN Microchip Technology, 93C86-E/SN Datasheet - Page 10

• Manufacturer Part Number: 93C86-E/SN
• Description: IC EEPROM 16KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93C86-E/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8 or 1K x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

93C76/86
4.0
TABLE 4-1:
4.1
A high level selects the device. A low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go
into Standby mode as soon as the programming cycle
is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a RESET status.
4.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C76/86.
Opcode, address and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but Start condition has not been detected,
any number of clock cycles can be received by the
device without changing its status (i.e., waiting for Start
condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
DS21132E-page 10
Name
ORG
CLK
V
V
DO
CS
PE
DI
CC
SS
PIN DESCRIPTIONS
Chip Select (CS)
Serial Clock (CLK)
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply
CKL
PIN FUNCTION TABLE
). This gives the controlling master
Function
CSL
) between
CKH
) and
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 1-3
through Table 1-6 for more details). CLK and DI then
become don't care inputs waiting for a new Start
condition to be detected.
4.3
Data In is used to clock in a Start bit, opcode, address
and data synchronously with the CLK input.
4.4
Data Out is used in the Read mode to output data
synchronously with the CLK input (T
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status
information is available when CS is high. It will be
displayed until the next Start bit occurs as long as CS
stays high.
4.5
When ORG is connected to V
organization is selected. When ORG is tied to V
x8 memory organization is selected. There is an
internal pull-up resistor on the ORG pin that will select
x16 organization when left unconnected.
4.6
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is
floated or tied to V
If the PE pin is tied to V
inhibited. There is an internal pull-up on this device that
enables programming if this pin is left floating.
Note:
Data In (DI)
Data Out (DO)
Organization (ORG)
Program Enable (PE)
CS must go low between consecutive
instructions, except when performing a
sequential read (Refer to Section 3.1
“Read” for more detail on sequential
reads).
CC
, the device can be programmed.
 2004 Microchip Technology Inc.
SS
, programming will be
CC
, the x16 memory
PD
after the
SS
, the