AT88SC0808C-MPTG Atmel, AT88SC0808C-MPTG Datasheet - Page 3

• Manufacturer Part Number: AT88SC0808C-MPTG
• Description: CRYPTOMEM 8KBIT 4 ZONE MOD P TWI
• Manufacturer: Atmel
• Series: CryptoMemory®r

Specifications of AT88SC0808C-MPTG

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8)
• Speed: 5MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: M2 P, Smart Card Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.
2.1.
2.2.
2.3.
2.4.
2024KS–SMEM–10/09
Figure 2.
SCL/CLK
Pin Descriptions
Supply Voltage (V
The V
Clock (SCL/CLK)
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The
nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f. When the
synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge
clock data out of the device.
Reset (RST)
The AT88SC0808C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset
sequence is activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal
pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC0808C does not support the synchronous answer-to-reset sequence
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of
other open drain or open collector devices. An external pull-up resistor should be connected between SDA and V
The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This
rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher
frequency operations while drawing higher average power. SDA/IO information applies to both asynchronous and
synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and
negative edge clock data out of the device.
SDA/IO
GND
V
RST
CC
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
Block Diagram
CC
Asynchronous
Management
Synchronous
ISO Interface
Reset Block
)
Interface
Power
Certification Unit
Answer to Reset
Authentication,
Encryption and
Data Transfer
Verification
Password
Generator
EEPROM
Random
AT88SC0808C
CC
3
.