24AA014H-I/MS Microchip Technology, 24AA014H-I/MS Datasheet - Page 9
![IC EEPROM 1KBIT 400KHZ 8MSOP](/photos/6/59/65932/mfg_150_c04-111_ms_8-msop_sml.jpg)
24AA014H-I/MS
Manufacturer Part Number
24AA014H-I/MS
Description
IC EEPROM 1KBIT 400KHZ 8MSOP
Manufacturer
Microchip Technology
Datasheet
1.24AA014H-ISN.pdf
(28 pages)
Specifications of 24AA014H-I/MS
Memory Size
1K (128 x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
100kHz, 400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Memory Configuration
128 X 8 / 64 X 16
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
1.7V To 5.5V
Memory Case Style
MSOP
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.0
6.1
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24AA014H/
24LC014H. After receiving another Acknowledge
signal from the 24AA014H/24LC014H, the master
device will transmit the data word to be written into the
addressed
24LC014H acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and the 24AA014H/24LC014H will not
generate Acknowledge signals during this time
(Figure 6-1). If an attempt is made to write to the
protected portion of the array when the hardware write
protection has been enabled,
acknowledge the command, but no data will be written.
The write cycle time must be observed even if write
protection is enabled.
6.2
The write-control byte, word address and the first data
byte are transmitted to the 24AA014H/24LC014H in the
same way as in a byte write. But instead of generating
a Stop condition, the master transmits up to 15
additional data bytes to the 24AA014H/24LC014H that
are temporarily stored in the on-chip page buffer and
will be written into the memory once the master has
transmitted a Stop condition. Upon receipt of each
word, the four lower order Address Pointer bits are
internally incremented by one.
FIGURE 6-1:
FIGURE 6-2:
© 2008 Microchip Technology Inc.
SDA Line
Bus Activity
Master
Bus Activity
SDA Line
Bus Activity
Master
Bus Activity
WRITE OPERATIONS
Byte Write
Page Write
memory
S
T
A
R
T
S
S
S
T
A
R
T
BYTE WRITE
PAGE WRITE
location.
Control
Byte
Control
Byte
The
the
A
C
K
device will
24AA014H/
Address (n)
Word
A
C
K
Preliminary
A
C
K
Address
Word
Data (n)
24AA014H/24LC014H
The higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
6.3
The WP pin must be tied to V
half of the array will be write-protected (40h-7Fh). If the
WP pin is tied to V
locations are allowed.
Note:
Write Protection
A
C
K
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary that the
application software prevent page write
operations that would attempt to cross a
page boundary.
A
C
K
Data (n +1)
SS
, write operations to all address
Data
A
C
K
CC
or V
Data (n + 15)
SS
DS22077B-page 9
. If tied to V
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P
CC
,