24LC21-I/SN Microchip Technology, 24LC21-I/SN Datasheet - Page 7

• Manufacturer Part Number: 24LC21-I/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC21-I/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1.6
After generating a Start condition, the bus master trans-
mits the slave address consisting of a 7-bit device code
‘1010’ for the 24LC21, followed by three “don’t care”
bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC21 (Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave
Acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-5:
 2004 Microchip Technology Inc.
Operation
Read
Write
1
Start
address
0
SLAVE ADDRESS
Control Code
SLAVE ADDRESS
1
all
1010
1010
CONTROL BYTE
ALLOCATION
the
0
time.
x
Chip Select
Read/Write
It
xxx
xxx
x
generates
R/W
x
R/W
A
1
0
an
4.0
4.1
Following the Start signal from the master, the slave
address (4 bits), the “don’t care” bits (3 bits) and the
R/W bit which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word
address and will be written into the address pointer of
the 24LC21. After receiving another Acknowledge
the data word to be written into the addressed mem-
ory location. The 24LC21 acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle, and during this time the
24LC21 will not generate Acknowledge signals
(Figure 4-1).
It is required that V
order to program the device. This applies to byte write
and page write operation. Note that V
while the device is in its self-timed program operation
and not affect programming.
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to eight data bytes to the
24LC21, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
signal from the 24LC21 the master device will transmit
WRITE OPERATION
Byte Write
Page Write
CLK
be held at a logic high level in
24LC21
DS21095J-page 7
CLK
can go low