ZLF645S2864GP0001T Maxim Integrated, ZLF645S2864GP0001T Datasheet - Page 83

• Manufacturer Part Number: ZLF645S2864GP0001T
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S2864GP0001T

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Interface Type: UART
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

Flash Control Register Definitions
19-4572; Rev 0; 4/09
Caution:
Mass Erase
Flash Control Register
Flash Controller prevents CPU accesses to the Flash’s Information block, the ICP can ini-
tiate a Page erase to page 3 of Information Area by a similar process as used for the main
memory. The only difference is that the ICP must first write bit 7 of the Flash Page Select
(PGS) register to a 1 before writing the page erase command to the Flash Control (FCTL)
register. For more details, see
The Flash main memory can also be Mass Erased using the Flash Controller, but only
through the ICP interface and not by the CPU. Mass Erasing the Flash memory sets all
bytes to the value
Flash Control register initiates the Mass Erase operation. If a Mass Erase operation is
performed using the ICP, bit 3 of the ICP Status register is polled to determine when the
operation is complete. When the Mass Erase is complete, the Flash Controller returns to its
locked state. You cannot mass erase the Information Area.
The Flash Controller must be unlocked using the Flash Control (FCTL) register (see
Table
memory. Writing values of
unlocks the Flash Controller, as long as the other conditions described in
Flash Controller For Flash Memory Accesses
Controller is unlocked, a Mass Erase initiated by the ICP, or Page Erase initiated by the
ICP or CPU can be executed by the Flash Controller by writing the appropriate command
value to this register. Execution of a Page Erase applies only to the active page selected in
Flash Page Select (FPS) register. Writing an invalid value or an invalid sequence returns
the Flash Controller to its locked state. The Write-only Flash Control register shares its
Register File address with the Read-only Flash Status register.
If either of the Flash Memory Protect Option Bits are set as defined in the Flash Op-
tion Bits section, a mass erase of the Flash's main memory must be performed before
Page 3 of the Flash's Information Area can be erased. These two operations must be
done when the device is at operating voltage. That is, if a mass erase is followed with
a power-down then power-up sequence, performing an Information Area Page 3 erase
will not erase its contents.
33) before the Flash Controller is enabled for programming or erasing the Flash
FFH
. With the Flash Controller unlocked, writing the value
73H
Table 34
and then
on page 77.
8CH
on page 70 have been met. When the Flash
sequentially to the Flash Control register
ZLF645 Series Flash MCUs
Flash Control Register Definitions
Product Specification
Enabling the
63H
to the
75