MC68HC908QT1VDW Freescale Semiconductor, MC68HC908QT1VDW Datasheet - Page 128

• Manufacturer Part Number: MC68HC908QT1VDW
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908QT1VDW

• Product Category: 8-bit Microcontrollers - MCU
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 1.5 KB
• Data Ram Size: 128 B
• On-chip Adc: No
• Operating Supply Voltage: 3.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOIC-8
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Timer Interface Module (TIM)
TRST — TIM Reset Bit
PS[2:0] — Prescaler Select Bits
14.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
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Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as a 0. Reset clears the TRST bit.
These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the
input to the TIM counter as
1 = Prescaler and TIM counter cleared
0 = No effect
Address: $0021
Address: $0022
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit 15
Bit 7
Bit 7
Bit 7
0
0
Figure 14-5. TIM Counter Registers (TCNTH:TCNTL)
PS2
0
0
0
0
1
1
1
1
TCNTH
TCNTL
= Unimplemented
Table 14-2
Bit 14
Bit 6
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
6
0
PS1
0
0
1
1
0
0
1
1
Table 14-2. Prescaler Selection
Bit 13
Bit 5
5
0
5
0
shows. Reset clears the PS[2:0] bits.
PS0
0
1
0
1
0
1
0
1
NOTE
NOTE
Bit 12
Bit 4
4
0
4
0
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
TIM Clock Source
Bit 11
Bit 3
3
0
3
0
PTA2/TCLK
Bit 10
Bit 2
2
0
2
0
Bit 9
Bit 1
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
0
0