CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 25

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Counter Operation
The CY7C09569V/09579V Dual-Port RAM (DPRAM) con-
tains on-chip address counters (one for each port) for the syn-
chronous members of the product family. Besides the main
x36 format, the right port allows bus matching (x18 or x9, user-
selectable). An internal sub-counter provides the extra ad-
dresses required to sequence out the 36-bit word in 18-bit or
9-bit increments. The sub-counter counts up in the “Little En-
dian” mode, and counts down if the user has chosen the “Big
Endian” mode. The address counter is required to be in incre-
ment mode in order for the sub-counter to sequence out the
second word (in x18 mode) or the remaining three bytes (in x9
mode).
For a x36 format (the only active format on the left port), each
address counter in the CY7C09579V uses addresses (A
For the right port (allowing for the bus-matching feature), a
maximum of two address bits (out of a 2-bit sub-counter) are
added.
A new read-back (Hold+Read Mode) feature has been added,
which is different between the left and right port due to the bus
matching feature provided only for the right port. In read-back
mode the internal address of the counter will be read from the
data I/Os as shown in Figure 1.
Bus Match Operation
The right port of the CY7C09569V/09579V 16K/32Kx36 dual-
port SRAM can be configured in a 36-bit long-word, 18-bit
Document #: 38-06054 Rev. *A
1. ADS
2. CNTEN
3. CNTRST
Note:
45. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
loading of that port’s burst counters if the corresponding
CNTEN
to stall the operation of the address input and utilize the
internal address generated by the internal counter for fast
interleaved memory applications; when asserted, the ad-
dress counter will increment on each positive transition of
that port’s clock signal.
______________
____________
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
_______
L/R
L/R
L/R
(pin #23/86) is a port’s address strobe, allowing the
Figure 1. Counter Operation Diagram
L/R
pin is active as well.
(pin #25/84) is a port’s count enable, provided
(pin #24/85) is a port’s burst counter reset.
CY7C09569V
CY7C09579V
ARRAY
RAM
0–14
).
word, or 9-bit byte format for data I/O. The data lines are divid-
ed into four lanes, each consisting of 9 bits (byte-size data
lines).
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) and Big Endian Select (BE) to select the bus width
(long-word, word, or byte) and data sequencing arrangement
for the right port of the dual-port device. A logic “0” applied to
both the Bus Match Select (BM) pin and to the Bus Size Select
(SIZE) pin will select long-word (36-bit) operation. A logic “1”
level applied to the Bus Match Select (BM) pin will enable
whether byte or word bus width operation on the right port I/Os
depending on the logic level applied to the SIZE pin. The level
of Bus Match Select (BM) must be static throughout normal
device operation.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement. A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
The Big Endian Select (BE) pin is a multiple-function pin during
word or byte bus selection (BM = 1). BE is used in Big Endian
Select mode to determine the order by which bytes (or words)
of data are transferred through the right data port. A logic “0”
on the BE pin will select Little Endian data sequencing ar-
rangement and a logic “1” on the BE pin will select a Big Endi-
an data sequencing arrangement. Under these circumstanc-
es, the level on the BE pin should be static throughout dual-
port operation.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit) opera-
tion. In this mode, the right port’s I/O operates essentially in an
identical fashion to the left port of the dual-port SRAM. How-
ever no Byte Select control is available. All 36 bits of the long-
word are shifted into and out of the right port’s I/O buffer stag-
es. All read and write timing parameters may be identical with
respect to the two data ports. When the right port is configured
for a long-word size, Big- Endian Select (BE) pin has no appli-
cation and their inputs are “Don’t Care”
user.
x36
/
Figure 2. Bus Match Operation Diagram
CY7C09569V
CY7C09579V
16K/32Kx36
Dual Port
9
/
9
/
9
/
9
/
BM SIZE
BE
[45]
CY7C09569V
CY7C09579V
for the external
x9, x18, x36
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