CY7C056V-15AC Cypress Semiconductor Corp, CY7C056V-15AC Datasheet - Page 12

• Manufacturer Part Number: CY7C056V-15AC
• Description: IC SRAM 16KX36 3.3V ASYN 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-15AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1172

Switching Waveforms
Document #: 38-06055 Rev. **
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
CE
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (t
29. t
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
31. To access RAM, CE
32. To access byte B
33. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
0
, CE
0
the bus for the required t
To access byte B
To access byte B
To access byte B
HA
, CE
R/W
R/W
is measured from the earlier of CE
OE
1
[31, 32]
1
[31, 32]
0
LOW and CE
0
1
2
3
, CE
, CE
, CE
, CE
0
= V
SD
0
0
0
0
1
= V
= V
= V
= V
HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
, CE
IL
IL
IL
IL
, B
, B
, B
, B
(continued)
t
t
1
SA
SA
=SEM = V
0
NOTE 34
1
2
3
= V
= V
= V
= V
0
SCE
/CE
IL
IL
IL
IL
, CE
, CE
, CE
, CE
or t
1
or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
IH
1
PWE
=SEM = V
.
1
1
1
=SEM = V
=SEM = V
=SEM = V
) of CE
t
[27, 28, 29, 35]
HZWE
[27, 28, 29, 30]
IH
0
=V
.
IH
IH
IH
[33]
IL
.
.
.
and CE
CHIP SELECT VALID
t
t
CHIP SELECT VALID
AW
AW
t
t
WC
WC
1
=V
t
t
SCE
PWE
IH
or SEM=V
[30]
IL
and B
t
t
PWE
SD
SD
0–3
or (t
LOW.
HZWE
+ t
SD
t
t
HA
HA
) to allow the I/O drivers to turn off and data to be placed on
t
t
HD
HD
t
LZWE
t
HZOE
NOTE 34
CY7C056V
CY7C057V
[33]
Page 12 of 23
PWE
.