CY7C1418BV18-167BZC Cypress Semiconductor Corp, CY7C1418BV18-167BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1418BV18-167BZC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1418BV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (2M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Truth Table
The truth table for the CY7C1418BV18, and CY7C1420BV18 follows.
Burst Address Table 
(CY7C1418BV18, CY7C1420BV18)
Write Cycle Descriptions
The write cycle description table for CY7C1418BV18 follows.
Notes
Document Number: 001-07033 Rev. *H
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, 
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1418BV18 and CY7C1420BV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
BWS
H
H
H
H
sequence in the burst.
symmetrically.
of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
0
BWS
H
H
H
H
L
L
L
L
1
L–H
L–H
L–H
L–H
First Address (External)
K
–
–
–
–
Operation
L–H During the data portion of a write sequence 
L–H During the data portion of a write sequence 
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence Both bytes (D
K
–
–
–
–
X..X0
X..X1
During the data portion of a write sequence  Both bytes (D
During the data portion of a write sequence 
Only the lower byte (D
Only the lower byte (D
During the data portion of a write sequence 
Only the upper byte (D
Only the upper byte (D
No data is written into the devices during this portion of a write operation.

represents rising edge.
[8:0]
[8:0]
[17:9]
[17:9]
Write Cycle Descriptions
) is written into the device, D
) is written into the device, D
Stopped
) is written into the device, D
) is written into the device, D
L-H
L-H
L-H
[2, 8]
K
[2, 3, 4, 5, 6, 7]
LD
H
L
L
X
table. BWS
Comments
0
R/W
, BWS
H
L
X
X
Second Address (Internal)
[17:9]
[17:9]
[8:0]
[8:0]
1
, BWS
[17:0]
[17:0]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D(A1) at K(t + 1)  D(A2) at K(t + 1) 
Q(A1) at C(t + 1) Q(A2) at C(t + 2) 
High-Z
Previous State
2
) are written into the device.
) are written into the device.
, and BWS
X..X1
X..X0
DQ
3
can be altered on different portions
CY7C1418BV18
CY7C1420BV18
High-Z
Previous State
Page 8 of 27
DQ
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