CY7C1168V18-375BZC Cypress Semiconductor Corp, CY7C1168V18-375BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1168V18-375BZC
• Description: IC SRAM 18MBIT 375MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1168V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
Application Example
Figure 1
Truth Table
The truth table for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows.
Notes
Document Number: 001-06620 Rev. *D
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
Read Cycle: (2.5 Cycle Latency)
Load address; wait two and a half cycle; read data on consec-
utive K and K rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Do K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
MASTER
shows two DDR-II+ used in an application.
BUS
Source CLK
Source CLK
Cycle Start
Addresses
R/W
DQ
Operation
DQ
A
↑
SRAM#1
LD R/W
represents rising edge.
Figure 1. Application Example
CQ/CQ
K
ZQ
K
Stopped
L-H
L-H
L-H
K
R = 250ohms
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the DLL to be
reset to lock to the desired frequency. During power up, when the
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
LD
H
X
L
L
R/W
H
X
X
L
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
DQ
D(A) at K (t + 1) ↑
Q(A) at K (t + 2)↑
High-Z
Previous State
A
SRAM#2
LD R/W
DQ
[2, 3, 4, 5, 6, 7]
CQ/CQ
K
ZQ
K
D(A + 1) at K (t + 1) ↑
Q(A + 1) at K (t + 3) ↑
High-Z
Previous State
R = 250ohms
DQ
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