CY7C1315JV18-300BZC Cypress Semiconductor Corp, CY7C1315JV18-300BZC Datasheet - Page 7

• Manufacturer Part Number: CY7C1315JV18-300BZC
• Description: IC SRAM SYNC 18KB QDR2 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315JV18-300BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-12562 Rev. *D
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
NC /144M
NC /288M
V
V
V
V
Pin Name
REF
DD
SS
DDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Echo Clock
Echo Clock
Reference
Ground
Output
Supply
Input-
Input
Input
Input
Input
Input
N/A
N/A
N/A
N/A
N/A
IO
(continued)
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off differs from those listed in this data sheet. For normal operation, this pin is
connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I mode when
the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR
I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Inputs to the Core of the Device.
Ground for the Device.
[x:0]
Switching Characteristics
Switching Characteristics
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Pin Description
CY7C1313JV18/CY7C1315JV18
CY7C1311JV18/CY7C1911JV18
on page 23.
on page 23.
DDQ
, which enables the
Page 7 of 27
[+] Feedback