CY7C1320BV18-250BZC Cypress Semiconductor Corp, CY7C1320BV18-250BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1320BV18-250BZC
• Description: IC SRAM 18MBIT 250MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1320BV18-250BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR-II. In the single clock mode,
Application Example
Figure 1
Document Number: 38-05621 Rev. *D
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
MASTER
ASIC)
(CPU
BUS
or
shows two DDR-II used in an application.
Source CLK#
Return CLK#
Cycle Start#
Return CLK
Source CLK
Addresses
SS
R/W#
DQ
to enable the SRAM to adjust its output
R = 50ohms
DQ
Vterm = 0.75V
Vterm = 0.75V
,
A
with V
LD#
DDQ
SRAM#1
R/W#
Figure 1. Application Example
= 1.5V. The
C C#
CQ/CQ#
K
K#
ZQ
R = 250ohms
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in
Characteristics
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock it to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. For information
refer to the application note
QDRII/DDRII/QDRII+/DDRII+.
CY7C1316BV18, CY7C1916BV18
CY7C1318BV18, CY7C1320BV18
on page 23.
DQ
A
LD#
AN5062, DLL Considerations in
SRAM#2
R/W#
C C#
CQ/CQ#
K
K#
ZQ
R = 250ohms
Page 9 of 31
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