CY7C131-25JXC Cypress Semiconductor Corp, CY7C131-25JXC Datasheet - Page 10
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CY7C131-25JXC
Manufacturer Part Number
CY7C131-25JXC
Description
IC SRAM 8KBIT 25NS 52PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Specifications of CY7C131-25JXC
Memory Size
8K (1K x 8)
Package / Case
52-PLCC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Access Time
25 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
170 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
2
Operating Supply Voltage
5 V
Memory Configuration
1K X 8
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
LCC
No. Of Pins
52
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C131-25JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C131-25JXCT
Manufacturer:
SIRF
Quantity:
672
Company:
Part Number:
CY7C131-25JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06002 Rev. *E
Notes
ADDRESS
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
ADDRESS
DATA
DATA
D
DATA
and for data to be placed on the bus for the required t
OUT
R/W
OE
CE
R/W
IN
OUT
CE
IN
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
t
HZOE
t
SA
(continued)
t
SA
SD
.
t
SCE
t
SCE
t
AW
t
AW
t
Either Port
HZWE
t
WC
t
WC
HIGH IMPEDANCE
t
PWE
DATA VALID
t
PWE
t
SD
PWE
HIGH IMPEDANCE
or t
t
DATA VALID
SD
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
t
HD
t
HD
t
LZWE
t
HA
t
HA
CY7C130, CY7C130A
CY7C131, CY7C131A
[16, 23]
[17, 24]
CY7C140, CY7C141
Page 10 of 19
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