93LC56A/SN Microchip Technology, 93LC56A/SN Datasheet - Page 11

• Manufacturer Part Number: 93LC56A/SN
• Description: IC EEPROM 2KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC56A/SN

• Memory Size: 2K (256 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 256 X 8
• Ic Interface Type: Microwire
• Clock Frequency: 3MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Package: 8SOIC N
• Interface Type: Serial-Microwire
• Density: 2 Kb
• Maximum Operating Frequency: 2 MHz
• Typical Operating Supply Voltage: 3.3|5 V
• Organization: 256x8
• Data Retention: 200(Min) Year
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC56A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
FIGURE 2-11:
© 2008 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
CS
V
DI
DI
CC
must be ≥4.5V for proper operation of WRAL.
Write All (WRAL)
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
1
1
High-Z
High-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
x
x
•••
•••
x
x
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be ≥4.5V for proper operation of WRAL.
CSL
•••
•••
).
D0
D0
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
T
CSL
CSL
T
WL
T
WL
Busy
Busy
T
T
SV
SV
Ready
Ready
Busy
Busy
H
H
DS21794F-page 11
status from DO.
IGH
IGH
T
T
-Z
status of the
-Z
CZ
CZ