93C56C-I/SN Microchip Technology, 93C56C-I/SN Datasheet - Page 8
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93C56C-I/SN
Manufacturer Part Number
93C56C-I/SN
Description
IC EEPROM 2KBIT 3MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.93AA56BT-IOT.pdf
(30 pages)
Specifications of 93C56C-I/SN
Memory Size
2K (256 x 8 or 128 x 16)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
3MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Memory Configuration
256 X 8 / 128 X 16
Ic Interface Type
3 Wire, Serial
Clock Frequency
3MHz
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
FIGURE 2-4:
DS21794F-page 8
CLK
CLK
DO
DO
CS
DI
V
CS
DI
CC
must be ≥4.5V for proper operation of ERAL.
Erase All (ERAL)
High-Z
High-Z
1
1
ERAL TIMING FOR 93AA AND 93LC DEVICES
ERAL TIMING FOR 93C DEVICES
0
0
0
0
1
1
0
0
x
x
•••
•••
The DO pin indicates the Ready/
device, if CS is brought high after a minimum of 250 ns
low (T
V
x
x
CC
Note:
T
T
must be ≥4.5V for proper operation of ERAL.
CSL
CSL
CSL
).
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
EC
T
T
T
SV
EC
SV
Check Status
Check Status
Busy
Busy
© 2008 Microchip Technology Inc.
Ready
Ready
Busy
Busy
status from DO.
High-Z
High-Z
status of the
T
T
CZ
CZ