MT46H32M32LFCM-6:A TR Micron Technology Inc, MT46H32M32LFCM-6:A TR Datasheet - Page 65

• Manufacturer Part Number: MT46H32M32LFCM-6:A TR
• Description: IC DDR SDRAM 1GBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M32LFCM-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 1G (32M x 32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 32Mx32
• Density: 1Gb
• Address Bus: 13b
• Access Time (max): 6.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 140mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1334-2

Figure 29: Data Output Timing –
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
DQ[15:8] and UDQS, collectively
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ[7:0] and LDQS, collectively
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
Notes:
UDQS
1.
2.
3. DQ transitioning after DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transitions and is defined as
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
LDQS
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
t
t
with DQS transition and ends with the last valid DQ transition.
er byte and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins
QH is derived from
3
3
4
4
4
4
4
4
4
7
7
7
7
7
7
7
7
4
4
4
6
7
7
6
T1
t
DQSQ,
t HP
1
t
QH, and Data Valid Window (x16)
t HP
t
CL or
1
t
t DQSQ
HP:
t QH
t DQSQ
T2
5
t QH
t
Data valid
2
t
QH =
window
CH clock transition collectively when a bank is active.
65
Data valid
T2
T2
5
T2
window
t HP
2
T2
T2
T2
1
t
HP -
t DQSQ
T2n
t QH
t DQSQ
Data valid
t QH
1Gb: x16, x32 Mobile LPDDR SDRAM
5
window
t
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t HP
QHS.
T2n
T2n
Data valid
T2n
5
window
2
1
T2n
T2n
T2n
T3
t DQSQ
t QH
t DQSQ
5
t QH
t HP
Data valid
2
window
Data valid
1
5
window
T3
T3
t
T3
2
T3
DQSQ window. LDQS defines the low-
T3
T3
T3n
t DQSQ
t DQSQ
t HP
t QH
t QH
1
Data valid
5
5
window
Data valid
2
2
window
T3n
T3n
T4
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T3n
T3n
T3n
T3n
READ Operation
t
QH -
t
DQSQ.