M25P32-VMW6TG NUMONYX, M25P32-VMW6TG Datasheet
M25P32-VMW6TG
Specifications of M25P32-VMW6TG
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M25P32-VMW6TG Summary of contents
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... More than 20 year data retention Packages – RoHS compliant Automotive certified parts available March 2010 32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface = 9 V) Rev 15 M25P32 VDFPN8 (ME) 8 × (MLP8) VFQFPN8 (MP) 6 × (MLP8) SO16 (MF) 300 mils width SO8W (MW) 208 mils www ...
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... Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR ...
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WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 11 ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SO8W and MLP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10 ...
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... Description The M25P32 Mbit ( Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment. The device enters this mode whenever the V Protect/Enhanced Program Supply Voltage pin (W/V The memory is organized as 64 sectors, each containing 256 pages ...
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... There is an exposed central pad on the underside of the MLP8 package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin- M25P32 V SS AI07483b Function M25P32 HOLD W/V 3 ...
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... Figure 3. SO16 connections Don’t Use 2. See Package mechanical 8/54 M25P32 HOLD W/V section for package dimensions, and how to identify pin-1. PP AI07484c ...
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Signal description 2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial data input (D) This input ...
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... If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA ...
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... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P32 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
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Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is ...
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... Memory organization The memory is organized as: 4,194,304 bytes (8 bits each) 64 sectors (512 Kbits, 65536 bytes each) 16384 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Table 3. Memory organization Sector 18/54 Address range 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h 3A0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1F0000h 1E0000h ...
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... Table 3. Memory organization (continued) Sector Address range 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...
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Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data bytes Read Data bytes at higher FAST_READ speed PP Page Program SE Sector Erase BE ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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... The Read Identification (RDID) instruction allows the device identification data to be read as explained here, with the data values shown in sequence. Manufacturer identification (1 byte): Numonyx value assigned by JEDEC. Device identification (2 bytes): assigned by the device manufacturer. – The first byte indicates the memory type. ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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... BP1, BP0) bits is set to 1, the relevant memory area (as defined in protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0 ...
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... The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed Status Register AI02282D Memory content (1) Protected area Unprotected area Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase instructions Protected against Ready to accept ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Address bits A23 to A22 are Don’t Care. 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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For optimized timings recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes. Chip Select (S) ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device ...
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... Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the old-style 8-bit Electronic Signature, whose value for the M25P32 is 15h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P32, is 15h. Figure 20. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in still ensures that the device is put into Standby Power mode ...
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Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 21. Power-up timing (max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed V CC (min) Reset State of the Device V WI Table 8. Power-up timing and V Symbol ...
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... Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 13. Capacitance Symbol Parameter C Output capacitance (Q) OUT C Input capacitance (other pins Sampled only, not 100% tested Table 14. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current ...
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Table 15. AC characteristics ( Applies only to products made with T9HX technology, identified with Process digit “4” Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, ...
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Table 15. AC characteristics ( Applies only to products made with T9HX technology, identified with Process digit “4” Test conditions specified in Symbol Alt. t Write Status Register cycle time W (7) t Page Program cycle time (256 bytes) PP ...
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Figure 24. Write Protect Setup and Hold timing during WRSR when SRWD=1 W/V PP tWHSL High Impedance Q Figure 25. Hold timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439b tHHCH AI02032 43/54 ...
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Figure 26. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 27. V PPH PPH W/V PP 44/54 tCLQV timing PP, SE, BE tVPPHSL tCH tCL LSB OUT tQLQH tQHQL End of PP, ...
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Package mechanical Figure 28. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package ...
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Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, package outline B SO-H 1. Drawing is not to scale. Table 17. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, mechanical data Symbol A ...
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Figure 30. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. Table 18. VFQFPN8 (MLP8) 8-lead Very thin Fine ...
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Figure 31. SO8W 8 lead Plastic Small Outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 19. SO8W 8 lead Plastic Small Outline, 208 mils body width, package mechanical data Symbol Typ ...
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... Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive envirnoment. The High Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest Numonyx sales office for a copy. 4. The lithography digit is present only in the automotive parts ordering scheme. M25P32 – (2) ...
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... For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 µm, process digit “4”), please contact your nearest Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...
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... Tested Parts from the non Auto Tested parts). Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P32 – ...
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... Plating Technology VDFPN8 package specifications updated (see mechanical). MLP8 5 × and SO8W packages added (see mechanical). VCC supply voltage Figure 4: Bus Master and memory devices on the SPI bus 9 explanation added below. Table 9: Absolute maximum Products in T9HX technology introduced (see characteristics (T9HX technology)) ...
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Table 22. Document revision history Date Revision Section 7: Power-up and Power-down Read Identification instruction modified in (RDID). Inserted UID and CFI content columns in (RDID) data-out Modified Data bytes for RDID instruction in 15-Jun-2007 10 Modified Q signal in ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...