MAX6841IUKD1+T Maxim Integrated, MAX6841IUKD1+T Datasheet - Page 13

• Manufacturer Part Number: MAX6841IUKD1+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6841, MAX6842, MAX6843, MAX6844, MAX6845r

Specifications of MAX6841IUKD1+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 0.9 V to 1.5 V
• Undervoltage Threshold: 1.35 V
• Overvoltage Threshold: 1.425 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 2 ms
• Supply Voltage - Max: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 571 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 8.1 uA
• Supply Voltage - Min: 0.75 V

Resistors in series with each B_P pin are recommend-
ed to limit the current in case there is a short between
adjacent B_P pins (see Figure 1).
The intermediate cell input bias current is typically
0.5nA. A 1kΩ resistor in series with any intermediate
cell moves the overvoltage trip point by typically 0.5mV,
which is insignificant compared to the ±25mV tolerance
in the overvoltage threshold. The top cell input bias cur-
rent during sampling period is typically 60µA. To
reduce the voltage change on the top cell input due to
sampling current, a filter resistance of 10Ω to 50Ω
should be added in series with the top cell. To attain
the desired filter characteristics, the capacitance
across the two top cell input pins should be 1µF.
The MAX1894/MAX1924 have internal ESD diodes on
each B_P pin for ESD protection up to 2kV. When high-
er ESD ratings are needed, capacitors (typically 0.1µF)
can be added across adjacent B_P pins (see Figure 1).
The RC filters improve the device immunity to ESD and
filter the noise spikes on B1P–B4P to prevent the
MAX1894/MAX1924 from being triggered and latched
prematurely by noise spikes.
SHDN and CTL allow external logic or microprocessors
to control the MAX1894/MAX1924 gate drivers. Drive
CTL high to turn off the three protection MOSFETs: DSO,
CGO, and TKO. Drive SHDN high to force the MAX1894/
MAX1924 into shutdown mode (with no charger applied).
SHDN and CTL do not affect the state machine. Toggling
these two pins does not change the state or reset any
fault conditions. If external control circuitry or a micro-
processor is not used, connect SHDN and CTL to PKN.
Table 3. MOSFET Selection
Si4947 (dual)
P-CHANNEL
MOSFETS
IRF7404
IRF7406
Protecting and Filtering Cell Inputs
Si4431
______________________________________________________________________________________
Control Pins SHDN and CTL
Advanced Li+ Battery-Pack Protectors
MAXIMUM DRAIN
CURRENT (A)
3.5 EA
6.7
5.8
5.8
Good layout is important to minimize the effects of
noise on the system and to ensure accurate voltage
and current measurements. Use the appropriate trace
widths for the high-current paths and keep traces short
to minimize parasitic inductance and capacitance.
Minimize current-sense resistor trace lengths and make
use of Kelvin connections to the resistor. Provide ade-
quate space and board area for the external MOSFETs
and sense resistor to dissipate the heat required. Place
RC filters close to B1P–B4P pins.
Figure 7. Pack-Short Current Fault
TRANSISTOR COUNT: 4259
NO
NO
NORMAL OPERATION
DSO, CGO, TKO = H
V
V
SRC
RSENSE
SET OD = 1
FOR 450µs
> V
Layout Considerations
B4P
Chip Information
> V
YES
PS_TH
+ 0.1V
YES
13