11AA010T-I/TT Microchip Technology, 11AA010T-I/TT Datasheet - Page 9

• Manufacturer Part Number: 11AA010T-I/TT
• Description: IC EEPROM 1KBIT 100KHZ SOT23-3
• Manufacturer: Microchip Technology

Specifications of 11AA010T-I/TT

• Memory Size: 1K (128 x 8)
• Package / Case: SOT-23-3, TO-236-3, Micro3™, SSD3, SST3
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz
• Interface: UNI/O™ (Single Wire)
• Voltage - Supply: 1.8 V ~ 5.5 V
• Organization: 128 x 8
• Interface Type: Serial
• Maximum Clock Frequency: 100 KHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 50 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 11AA010T-I/TTTR

3.6
The 11XX features a low-power Standby mode during
which the device is waiting to begin a new command.
A high-to-low transition on SCIO will exit low-power
mode and prepare the device for receiving the start
header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
• Reception of a standby pulse
3.7
The 11XX features an Idle mode during which all serial
data is ignored until a standby pulse occurs. Idle mode
will be entered upon the following conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
• Missed edge transition
• Reception of a MAK following a
• Reception of a MAK following the data byte of a
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
3.8
At the beginning of every command, the 11XX utilizes
the start header to determine the master’s bus clock
period. This period is then used as a reference for all
subsequent communication within that command.
The 11XX features re-synchronization circuitry which
will monitor the position of the middle data edge during
each MAK bit and subsequently adjust the internal time
reference in order to remain synchronized with the
master.
There are two variables which can cause the 11XX to
lose synchronization. The first is frequency drift,
defined as a change in the bit period, T
edge jitter, which is a single occurrence change in the
position of an edge within a bit period, while the bit
period itself remains constant.
© 2008 Microchip Technology Inc.
tion of a command)
Note: In the case of the
Write, WRSR, SETAL, and ERAL during a write
cycle.
SETAL
WRSR
command
Device Standby
Device Idle
Synchronization
, or
ERAL
upon receipt of the NoMAK, assuming all
other write requirements have been met.
ERAL
commands, the write cycle is initiated
command byte
WRITE
WREN
,
WRSR
E
. The second is
,
WRDI
,
SETAL
,
, or
Preliminary
3.8.1
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, F
specifies the maximum tolerable change in bus fre-
quency per byte. F
quency deviation within an operation (i.e., from the end
of the start header until communication is terminated
for that operation). The start header at the beginning of
the next operation will reset the re-synchronization cir-
cuitry and allow for another F
drift.
3.8.2
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization cir-
cuitry is designed to provide some tolerance for edge
jitter.
The 11XX adjusts its phase every MAK bit, so T
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against T
jitter compliance.
Note: Because the 11XX only re-synchronizes
11AAXXX/11LCXXX
during the MAK bit, the overall ability to
remain synchronized depends on a combi-
nation of frequency drift and edge jitter (i.e.,
if the MAK bit edge is experiencing the max-
imum allowable edge jitter, then there is no
room for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no edge
jitter can be present.
FREQUENCY DRIFT
EDGE JITTER
DEV
specifies the overall limit in fre-
DEV
DRIFT
amount of frequency
and F
DS22067D-page 9
IJIT
to determine
DEV
. F
DRIFT
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