CY7C1474BV25-167BGI Cypress Semiconductor Corp, CY7C1474BV25-167BGI Datasheet

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... SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. ...

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... CE2 CE3 ZZ Logic Block Diagram – CY7C1472BV25 (4M x 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ZZ Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY ...

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... Logic Block Diagram – CY7C1474BV25 (1M x 72) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ZZ Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 ADDRESS REGISTER A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ...

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... SS V DDQ 11 DQc 12 DQc CY7C1470BV25 (2M × 36 DQd 18 DQd 19 V DDQ DQd 22 DQd 23 DQd 24 DQd DDQ 27 DQd 28 DQd 29 DQPd 30 Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Figure 1. 100-Pin TQFP Pinout NC 1 DQPb DQb 79 DQb DDQ DDQ DQb 75 DQb DQb DQb 8 73 DQb DQb DDQ V ...

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... DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 CY7C1470BV25 ( CEN CLK TDI A1 TDO TCK TMS CY7C1472BV25 ( CEN 3 ...

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... DQc DQc H DQc DQc J DQc DQc DQh DQh M DQh DQh N DQh DQh P DQh DQh R DQPd DQPh T DQd DQd U DQd DQd NC/144M V DQd DQd W DQd DQd Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 CY7C1474BV25 (1M × 72 ADV/ BWS BWS BWS BWS NC/576M NC/ DDQ DDQ DD DD ...

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... Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. Output Synchronous TDI JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. Synchronous Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Pin Description controls DQ and DQP controls DQ ...

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... On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ /DQP a,b,c,d CY7C1472BV25, CY7C1474BV25). In addition, the address for the subsequent CY7C1470BV25 Single Read for CY7C1470BV25, DQ /DQP a,b,c,d a,b ...

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... CY7C1472BV25, DQ /DQP a,b,c,d,e,f,g,h CY7C1474BV25) (or a subset for Byte Write operations, see “Partial Write Cycle Description” on page 11 latched into the device and the Write is complete. The data written during the Write operation is controlled by BW (BW for CY7C1470BV25, BW for CY7C1472BV25, and ...

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... Table 4. Truth Table The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Address Operation Deselect Cycle Continue Deselect Cycle Read Cycle External (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read External (Begin Burst) Dummy Read (Continue Burst) Write Cycle External (Begin Burst) ...

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... Table 5. Partial Write Cycle Description The partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Function (CY7C1470BV25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...

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... IO ring when these instruc- tions are executed. Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls ...

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... Test Data-In (TDI) Test Data-Out (TDO) Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board ...

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... Capture Hold after Clock Rise CH Notes 9. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 10. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Description / ns CY7C1470BV25 Min Max Unit ...

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... Table 7. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order–165FBGA Boundary Scan Order–209BGA Note 11. All voltages refer to V (GND). SS Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Figure 5. 2.5V TAP AC Output Load Equivalent to 2.5V SS TDO [11] Test Conditions I = –1.0 mA 2.5V OH DDQ = –100 μ ...

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... Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Description 165-Ball ID Bit # 165-Ball J11 P2 42 K10 R4 43 J10 P6 44 H11 R6 45 G11 R8 46 F11 P3 47 E11 P4 48 D10 P8 49 D11 P9 50 C11 P10 51 G10 R9 52 F10 R10 53 E10 R11 54 A9 N11 55 B9 M11 56 A10 L11 ...

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... Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 209-Ball ID Bit # 209-Ball U10 T2 58 T11 U1 59 T10 ...

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... DD 13 assumes a linear ramp from Power-up DD 14. The operation current is calculated with 50% read cycle and 50% write cycle. Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA Operating Range Range Commercial ...

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... Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms 2.5V IO Test Load OUTPUT Z = 50Ω 50Ω 1.25V L (a) Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Test Conditions Max Device Deselected, 4.0-ns cycle, 250 MHz DD ≤ 0. 5.0-ns cycle, 200 MHz − 0.3V, V > DDQ 1/t 6 ...

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... These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 18. This parameter is sampled and not 100% tested. Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 = 2.5V. Test conditions shown in (a) of DDQ –250 ...

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... WRITE WRITE D(A1) D(A2) Notes 19. For this waveform ZZ is tied LOW. 20. When CE is LOW LOW HIGH, and 21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear Interleaved).Burst operations are optional. Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 [19, 20, 21] Figure 6. Read/Write Timing ...

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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 23. Device must be deselected when entering ZZ mode. See 24. IOs are in High-Z when exiting ZZ sleep mode. Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 [19, 20, 22] Figure 7. NOP, STALL and DESELECT Cycles 3 ...

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... CY7C1470BV25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1472BV25-167BZI CY7C1470BV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1472BV25-167BZXI CY7C1474BV25-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474BV25-167BGXI 200 CY7C1470BV25-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1472BV25-200AXC CY7C1470BV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( ...

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... CY7C1472BV25-250BZXI CY7C1474BV25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474BV25-250BGXI Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 Part and Package Type 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free CY7C1470BV25 Operating ...

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... R 0.08 MIN. 0° MIN. 0.20 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP SEATING PLANE STAND-OFF 0.05 MIN. NOTE: ...

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... Package Diagrams (continued) Figure 10. 165-Ball FBGA ( 1.4 mm), 51-85165 TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 001-15032 Rev. *D CY7C1472BV25, CY7C1474BV25 0.15(4X) CY7C1470BV25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 51-85165-*A Page [+] Feedback ...

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... Package Diagrams (continued) Figure 11. 209-Ball FBGA ( 1.76 mm), 51-85167 Document #: 001-15032 Rev. *D CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 51-85167-** Page [+] Feedback ...

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... Document History Page Document Title: CY7C1470BV25/CY7C1472BV25/CY7C1474BV25, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15032 REV. ECN No. Issue Date Orig. of Change ** 1032642 See ECN VKN/KKVTMP *A 1562503 See ECN VKN/AESA *B 1897447 See ECN VKN/AESA *C 2082487 See ECN ...