MAX6324HUT26-T Maxim Integrated, MAX6324HUT26-T Datasheet - Page 10

• Manufacturer Part Number: MAX6324HUT26-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6323, MAX6324r

Specifications of MAX6324HUT26-T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 27 uA
• Supply Voltage - Min: 1.2 V

µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
Figure 9. Watchdog Flow Diagram
Figure 10. WDPO to MR Loopback Circuit
10
______________________________________________________________________________________
V
CC
SUBROUTINE OR
PROGRAM LOOP
SET WDI HIGH
SET WDI
RETURN
START
LOW
END
*MAX6324 ONLY
500pF
MR
MAX6323
MAX6324
GND
V
CC
RESET
WDPO
WDI
An error detected by the watchdog often indicates that
a problem has occurred in the µP code execution. This
could be a stalled instruction or a loop from which the
processor cannot free itself. If the µP will still respond
to a nonmaskable input (NMI), the processor can be
redirected to the proper code sequence by connecting
the WDPO output to an NMI input. Internal RAM data
should not be lost, but it may have been contaminated
by the same error that caused the watchdog to time
out.
If the processor will not recognize NMI inputs, or if the
internal data is considered potentially corrupted when
a watchdog error occurs, the processor should be
restarted with a reset function. To obtain proper reset
timing characteristics, the WDPO output should be
connected to the MR input, and the RESET output
should drive the µP RESET input (Figure 10). The short
1ms WDPO pulse output will assert the manual reset
input and force the RESET output to assert for the full
reset timeout period (100ms min). All internal RAM data
is lost during the reset period, but the processor is
guaranteed to begin in the proper operating state.
*R
PULLUP
RESET
I/O
WDPO to MR Loopback
V
µP
CC