CY7C1520JV18-300BZXC Cypress Semiconductor Corp, CY7C1520JV18-300BZXC Datasheet
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY7C1520JV18-300BZXC
Specifications of CY7C1520JV18-300BZXC
Available stocks
Related parts for CY7C1520JV18-300BZXC
CY7C1520JV18-300BZXC Summary of contents
Page 1
... CY7C1518JV18 and two 36-bit words in the case of CY7C1520JV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same ...
Page 2
... Logic Block Diagram (CY7C1527JV18 (21:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...
Page 3
... Logic Block Diagram (CY7C1518JV18) Burst A0 Logic (21:0) A Address (21:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1520JV18) Burst A0 Logic (20:0) A Address (20:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-12559 Rev. *C ...
Page 4
... Pin Configuration The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...
Page 5
... Pin Configuration The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC ...
Page 6
... CY7C1518JV18 – the input to the burst counter. These are incremented in a linear fashion internally. 22 address inputs are needed to access the entire memory array. CY7C1520JV18 – the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected ...
Page 7
... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Description output impedance are set to 0.2 x RQ, where resistor connected [x:0] , which enables the DDQ Page [+] Feedback ...
Page 8
... Functional Overview The CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V behaves in DDR-I mode with a read latency of one clock cycle. ...
Page 9
... Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 DDR-II referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In single clock mode generated with respect to K and CQ is generated with respect to K ...
Page 10
... Device powers up deselected with the outputs in a tri-state condition CY7C1518JV18 and CY7C1520JV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. On CY7C1516JV18 and CY7C1527JV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’. ...
Page 11
... L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1520JV18 follows. BWS BWS BWS BWS ...
Page 12
... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...
Page 13
... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...
Page 14
... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...
Page 15
... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 0 Bypass Register Instruction Register ...
Page 16
... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V ...
Page 17
... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Value CY7C1527JV18 CY7C1518JV18 001 001 00000110100 00000110100 ...
Page 18
... Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...
Page 19
... DDQ DOFF Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 DLL Constraints DLL uses K clock as its synchronizing input. The input must I have low phase jitter, which is specified as t The DLL functions at frequencies down to 120 MHz the input clock is unstable and the DLL is enabled, then the ...
Page 20
... RQ < 350:. OL DDQ 18. V (min) = 0.68V or 0.46V , whichever is larger, V REF DDQ Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA Operating Range Range Commercial DD Industrial + 0.3V DDQ + 0 ...
Page 21
... 250: (a) Notes 19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Test Conditions T = 25qC MHz 1.8V DDQ Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51 ...
Page 22
... CHZ CLZ 23. At any voltage and temperature t is less than t CHZ Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Description [20] [21] [22, 23] [22, 23] is the time that the power is supplied above V min initially before a read or write operation can be initiated. ...
Page 23
... Outputs are disabled (High-Z) one clock cycle after a NOP. 26. In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 [24, 25, 26] NOP NOP ...
Page 24
... Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 300 CY7C1516JV18-300BZC CY7C1527JV18-300BZC CY7C1518JV18-300BZC CY7C1520JV18-300BZC CY7C1516JV18-300BZXC CY7C1527JV18-300BZXC CY7C1518JV18-300BZXC CY7C1520JV18-300BZXC CY7C1516JV18-300BZI CY7C1527JV18-300BZI CY7C1518JV18-300BZI CY7C1520JV18-300BZI CY7C1516JV18-300BZXI CY7C1527JV18-300BZXI CY7C1518JV18-300BZXI CY7C1520JV18-300BZXI Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
Page 25
... Package Diagram Figure 4. 165-ball FBGA ( 1.40 mm), 51-85195 Document Number: 001-12559 Rev. *C CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 51-85195-*A Page [+] Feedback ...
Page 26
... Document History Page Document Title: CY7C1516JV18/CY7C1527JV18/CY7C1518JV18/CY7C1520JV18, 72-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number: 001-12559 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 808457 See ECN VKN *A 1273883 See ECN VKN *B 1462589 See ECN VKN/AESA *C 2189567 See ECN VKN/AESA © Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...