CY7C057V-12AC Cypress Semiconductor Corp, CY7C057V-12AC Datasheet - Page 20

• Manufacturer Part Number: CY7C057V-12AC
• Description: IC SRAM 32KX36 3.3V ASYN 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C057V-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1.152M (32K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1173

Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can
be configured in a 36-bit long-word, 18-bit word, or 9-bit byte
format for data I/O. The data lines are divided into four lanes,
each consisting of 9 bits (byte-size data lines).
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) to select bus width (long-word, word, or byte) for the
right port of the dual-port device. The data sequencing ar-
rangement is selected using the Word Address (WA) and Byte
Address (BA) input pins. A logic “0” applied to both the Bus
Match Select (BM) pin and to the Bus Size Select (SIZE) pin
will select long-word (36-bit) operation. A logic “1” level applied
to the Bus Match Select (BM) pin will enable either byte or
word bus width operation on the right port I/Os depending on
the logic level applied to the SIZE pin. The level of Bus Match
Select (BM) must be static throughout device operation.
Normally, the Bus Size Select (SIZE) pin would have no stan-
dard-cycle application when BM = LOW and the device is in
long-word (36-bit) operation. A “special” mode has been add-
ed however to disable ALL right port I/Os while the chip is
active. This I/O disable mode is implemented when SIZE is
forced to a logic “1” while BM is at a logic “0”. It allows the bus-
matched port to support a chip enable “Don’t Care” semaphore
read/write access similar to that provided on the left port of the
device when all Byte Select (B
ed.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement). A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Se-
lect (SIZE) must also be static throughout normal device oper-
ation.
Note:
Document #: 38-06055 Rev. **
51. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
x36
/
16K/32Kx36
CY7C056V
CY7C057V
Dual Port
9
/
9
/
9
/
9
/
0–3
) control inputs are deselect-
BA WA
BM SIZE
x9, x18, x36
/
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit) opera-
tion. In this mode, the right port’s I/O operates essentially in an
identical fashion as does the left port of the dual-port SRAM.
However no Byte Select control is available. All 36 bits of the
long-word are shifted into and out of the right port’s I/O buffer
stages. All read and write timing parameters may be identical
with respect to the two data ports. When the right port is con-
figured for a long-word size, Word Address (WA), and Byte
Address (BA) pins have no application and their inputs are
“Don’t Care”
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus SIze Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O
(WA) pin during word bus size operation determines whether
the most-significant or least-significant data bits are ported
through the I/O
lect fashion (note that when the right port is configured for word
size operation, the Byte Address pin has no application and its
input is “Don’t Care”
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, data is ported through
I/O
group is selected according to the levels applied to the Word
Address (WA) and Byte Address (BA) input pins.
Device operation is accomplished by treating the Word Ad-
dress (WA) pin and the Byte Address (BA) pins as additional
address inputs having standard cycle address and data set-
up/hold times. When transferring data in byte (9-bit) bus match
format, the unused I/O
0R–8R
I/O
I/O
I/O
I/O
27R–35R
18R–26R
I/Os
9R–17R
0R–8R
in four groups of 9-bit bytes. A particular 9-bit byte
0R–17R
[51]
0R–17R
for the external user.
. The level applied to the Word Address
Upper-MSB
Lower-MSB
Upper-MSB
Lower-MSB
[51]
pins in an Upper Word/Lower Word se-
9R–35R
Rank
).
pins are three-stated.
18R–35R
WA
pins are three-stated.
1
1
0
0
CY7C056V
CY7C057V
Page 20 of 23
BA
1
0
1
0