CY7C1250V18-333BZC Cypress Semiconductor Corp, CY7C1250V18-333BZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1250V18-333BZC
• Description: IC SRAM 36MBIT 333MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1250V18-333BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 333MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS compliant by exemption

Pin Definitions
Document Number: 001-06348 Rev. *E
DQ
LD
BWS
BWS
A
R/W
QVLD
K
K
CQ
CQ
ZQ
DOFF
Pin Name
[x:0]
0
2
, BWS
, BWS
1
3
,
Input/Output-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Valid output
indicator
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
Input
Input
I/O
Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid
write operations. These pins drive out the requested data during a read operation. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q
CY7C1248V18 − DQ
CY7C1250V18 − DQ
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD
must meet the setup and hold times around edge of K.
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1248V18 − BWS
CY7C1250V18 − BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 18 (2 arrays each of 1M x 18) for CY7C1248V18, and 1M x 36 (2 arrays each of
512K x 36) for CY7C1250V18.
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read
when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous data being presented to the device
and to drive out data through Q
clock (K) of the DDR II+. The timing for the echo clocks is shown in
page
clock (K) of the DDR II+. The timing for the echo clocks is shown in
page
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timing in the DLL turned off operation is different from that listed in this data sheet. For normal
operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The
device behaves in DDR I mode when the DLL is turned off. In this mode, the device can be operated
at a frequency of up to 167 MHz with DDR I timing.
20.
20.
[35:27]
[x:0]
.
are automatically tristated.
[17:0]
[35:0]
0
0
controls D
controls D
[x:0]
[x:0]
[x:0]
when in single clock mode. All accesses are initiated on the rising
[8:0]
[8:0]
when in single clock mode.
output impedance are set to 0.2 x RQ, where RQ is a resistor
, BWS
and BWS
Pin Description
1
controls D
1
controls D
[17:9]
[17:9].
, BWS
2
“Switching Characteristics” on
“Switching Characteristics” on
controls D
CY7C1248V18
CY7C1250V18
[26:18]
and BWS
Page 4 of 24
DDQ
, which
3
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