CY7C1061AV33-10ZXC Cypress Semiconductor Corp, CY7C1061AV33-10ZXC Datasheet - Page 13

• Manufacturer Part Number: CY7C1061AV33-10ZXC
• Description: IC SRAM 16MBIT 10NS 54TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1061AV33-10ZXC

• Memory Size: 16M (1M x 16)
• Package / Case: 54-TSOP II
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 10 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 275 mA
• Organization: 1 M x 16
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3.3 V
• Density: 16Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 20b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 54
• Word Size: 16b
• Number Of Words: 1M
• Memory Configuration: 1M X 16
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1983; CY7C1061AV33-10ZXC

Document History Page
Document #: 38-05256 Rev. *K
Document Title: CY7C1061AV33 16-Mbit (1 M × 16) Static RAM
Document Number: 38-05256
Revision
*G
*A
*B
*C
*D
*E
*H
*K
*F
*J
**
*I
2897049
3109147
3160428
3222127
113725
117058
117989
120383
124439
492137
508117
877322
ECN
Submission
12/13/2010
04/11/2011
See ECN
See ECN
See ECN
03/28/02
07/31/02
08/30/02
11/06/02
03/22/10
02/02/11
2/25/03
Date
Change
Orig. of
PRAS
PRAS
MEG
DFP
DFP
DFP
NXR
NXR
VKN
KAO
KAO
NSL
New Data Sheet
Removed 15-ns bin
Added 8-ns bin
Changed Icc for 8, 10, 12 bins
t
Load Cap Comment changed (for Tx line load)
t
Changed some 8-ns bin numbers (t
Removed hz<lz comments from data sheet
Final data sheet
Added note 3 to “AC Test Loads and Waveforms” and note 7 to t
Updated Input/Output Caps (for 48BGA only) to 8 pF/10 pF and for the
54-pin TSOP to 6/8 pF
Changed ISB1 from 100 mA to 70 mA
Shaded fBGA production ordering information
Corrected Block Diagram on page #1
Removed 8 ns speed bin
Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration
Included Note #1 and 2 on page #2
Changed the description of I
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
Updated FBGA Pin Configuration
Updated Ordering Information table
Updated Ordering Information table
package diagrams, links in Sales, Solutions and Legal Information
Added
Ordering information updates.
Template and style updates.
Added
Removed inactive parts from the ordering information table. Updated
power
SD
changed to 5.5 ns for the 10-ns bin
changed from 1 s to 1 ms.
Ordering Code
Acronyms
and
Units of
Definitions.
Description of Change
IX
from Input Load Current to Input Leakage
Measure.
HZ
, t
DOE
, t
DBE
CY7C1061AV33
)
Page 13 of 14
pu
and t
pd
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