M28W320CB90N6 NUMONYX, M28W320CB90N6 Datasheet - Page 10

• Manufacturer Part Number: M28W320CB90N6
• Description: IC FLASH 32MBIT 90NS 48TSOP
• Manufacturer: NUMONYX

Specifications of M28W320CB90N6

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (2M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1694

M28W320CT, M28W320CB
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
mode. When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V
Down is enabled and the protection status of the
block cannot be changed. When Write Protect is at
V
be locked or unlocked. (refer to Table 6, Read Pro-
tection Register and Protection Register Lock).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
10/53
IH
, the Lock-Down is disabled and the block can
IL
and Reset is at V
IH
the device is in active
IH
the memory is
IL
, the Lock-
IL
,
state. When Reset is at V
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
Enable or a change of the address is required to
ensure valid data outputs.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
power supply to the I/O pins and enables all Out-
puts to be powered independently from V
can be tied to V
V
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see Table 14, DC Charac-
teristics for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V
power supply pin. In this condition V
stable until the Program/Erase algorithm is com-
pleted (see Table 16 and 17).
V
measurements.
Note: Each device in a system should have
V
pacitor close to the pin. See Figure 9, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficient to carry the required V
program and erase currents.
DD
PP
PP
SS
DD
DDQ
PP
PP
, V
Ground. V
is seen as a control input. In this case a volt-
Program Supply Voltage. V
Supply Voltage. V
Supply Voltage. V
is kept in a low voltage range (0V to 3.6V)
is in the range 11.4V to 12.6V it acts as a
DDQ
and V
DD
PPLK
SS
PP
or can use a separate supply.
is the reference for all voltage
decoupled with a 0.1µF ca-
gives an absolute protection
IH
DD
, the device is in normal
PP
DDQ
provides the power
can be applied in
provides
PP
PP
PP
> V
PP
DD
is both a
DD
must be
and the
PP1
is only
. V
DDQ
the
en-
PP