CY7C1356CV25-166AXC Cypress Semiconductor Corp, CY7C1356CV25-166AXC Datasheet

Page 1

... CY7C1356CV25) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE asynchronous output enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence ...

Page 2

... Logic Block Diagram–CY7C1356CV25 (512 K × 18) ADDRESS A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Document Number: 38-05537 Rev A1 BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER WRITE REGISTRY S MEMORY E AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT ...

Page 3

... TAP Timing ...................................................................... 14 TAP AC Switching Characteristics ............................... 14 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 TAP DC Electrical Characteristics And Operating Conditions ............................................. 15 Identification Register Definitions ................................ 15 Scan Register Sizes ....................................................... 15 Identification Codes ....................................................... 15 Boundary Scan Exit Order (256 K × 36) ........................ 16 Boundary Scan Exit Order (512 K × ...

Page 4

... DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354CV25 CY7C1356CV25 166 MHz Unit 3.5 ns 180 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa ...

Page 5

... DDQ Document Number: 38-05537 Rev. *K 119-ball BGA Pinout CY7C1354CV25 (256 K × 36 NC/18M ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1356CV25 (512 K × 18 NC/18M ADV/ CLK CEN DQP MODE NC/36M A TMS TDI TCK TDO CY7C1354CV25 CY7C1356CV25 DDQ CE NC ...

Page 6

... V b DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05537 Rev. *K 165-ball FBGA Pinout CY7C1354CV25 (256 K × 36 CEN CLK TDI A1 TDO TCK TMS CY7C1356CV25 (512 K × 18 CEN CLK TDO A TDI A A0 TCK TMS CY7C1354CV25 CY7C1356CV25 ADV/LD OE NC/18M DQP SS DDQ b ...

Page 7

... DQ a and DQP , BW controls DQ and DQP select/deselect the device select/deselect the device select/deselect the device. 2 –DQ are placed in a tri-state condition. The outputs are controlled DQP is controlled controlled CY7C1354CV25 CY7C1356CV25 and DQP , BW controls DQ and DQP During [a:d]. , DQP is controlled Page [+] Feedback ...

Page 8

... On the next clock rise the data presented to DQ (DQ /DQP a,b,c,d CY7C1356CV25) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. The data written during the write operation is controlled by BW ...

Page 9

... The output enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQ /DQP for CY7C1354CV25 and DQ a,b,c,d a,b,c,d CY7C1356CV25) inputs. Doing so will tri-state the output drivers safety precaution, DQ and DQP (DQ CY7C1354CV25 and DQ /DQP for CY7C1356CV25) are a,b a,b automatically tri-stated during the data portion of a write cycle, regardless of the state of OE ...

Page 10

... Write bytes d, a Write bytes d, b Write bytes Write bytes d, c Write bytes Write bytes Write all bytes Partial Write Cycle Description Function (CY7C1356CV25) Read Write – no bytes written Write byte a − (DQ and DQP ) a a Write byte b – (DQ and DQP ...

Page 11

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354CV25/CY7C1356CV25 incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance ...

Page 12

... TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the SRAM clock CY7C1354CV25 CY7C1356CV25 Page [+] Feedback ...

Page 13

... Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. ...

Page 14

... CS CH 15. Test conditions are specified using the load in TAP AC test Conditions. t Document Number: 38-05537 Rev CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED Description / ns CY7C1354CV25 CY7C1356CV25 TDOV Min Max Unit 50 – ns – 20 MHz 20 – – ns – – – ...

Page 15

... CY7C1356CV25 000 000 Reserved for version number. 01011001000010110 Reserved for future use. 00000110100 Allows unique identification of SRAM vendor Indicate the presence register. Bit Size (× 36 Description CY7C1354CV25 CY7C1356CV25 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.0 – V 2.1 – V – 0.4 V – ...

Page 16

... Boundary Scan Exit Order (256 K × 36) Bit # 165-ball B10 52 A10 53 C11 54 E10 55 F10 56 G10 57 D10 58 D11 59 E11 60 F11 61 G11 62 H11 63 J10 64 K10 65 L10 66 M10 67 J11 68 K11 69 L11 M11 N11 R11 R10 P10 CY7C1354CV25 CY7C1356CV25 119-ball ID 165-ball Not Bonded Not Bonded (Preset to 1) (Preset Page [+] Feedback ...

Page 17

... Not Bonded (Preset R11 67 R10 P10 CY7C1354CV25 CY7C1356CV25 119-ball ID 165-ball ID Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset ...

Page 18

... All speed grades DD ≥ V ≤ /2), undershoot: V (AC)> –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1354CV25 CY7C1356CV25 Ambient Temperature DDQ 0 °C to +70 °C 2.5 V ± 5% –40 °C to +85 °C Min Max Unit 2.375 2.625 V 2.375 2.0 – ...

Page 19

... 2 2 DDQ 5 5 100 TQFP Test Conditions Package 29.41 6. 1667Ω 2.5V V DDQ GND 1538Ω INCLUDING JIG AND SCOPE (b) CY7C1354CV25 CY7C1356CV25 119 BGA 165 FBGA Unit Max Max 119 BGA 165 FBGA Unit Package Package 34.1 16.8 °C/W 14 3.0 °C/W ...

Page 20

... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1354CV25 CY7C1356CV25 –200 –166 Unit Min Max Min Max 1 – ...

Page 21

... DOH CLZ D(A1) D(A2) Q(A3) D(A2+1) BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1354CV25 CY7C1356CV25 OEV CHZ Q(A4) Q(A4+1) D(A5) t OEHZ t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

Page 22

... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05537 Rev D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE is LOW. When CE is HIGH HIGH CY7C1354CV25 CY7C1356CV25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED is LOW HIGH Page ...

Page 23

... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 33. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05537 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1354CV25 CY7C1356CV25 Page [+] Feedback ...

Page 24

... Speed Package (MHz) Ordering Code Diagram 166 CY7C1354CV25-166AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free CY7C1356CV25-166AXC CY7C1354CV25-166BZC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) 200 CY7C1354CV25-200AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-free Ordering Code Definitions CY7C 135X C ...

Page 25

... Package Diagrams Figure 1. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 51-85050 *C Page [+] Feedback ...

Page 26

... Figure 2. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 51-85115 *C Page [+] Feedback ...

Page 27

... Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 51-85180 *C Page [+] Feedback ...

Page 28

... TDI test data input TMS test mode Select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05537 Rev. *K CY7C1354CV25 CY7C1356CV25 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...

Page 29

... Document History Page Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05537 REV. ECN No. Issue Date Change ** 242032 See ECN *A 278969 See ECN *B 284929 See ECN *C 323636 See ECN *D 332879 See ECN *E 357258 ...

Page 30

... C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 8, 2010 CY7C1354CV25 CY7C1356CV25 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...