CY7C1361C-133AXI Cypress Semiconductor Corp, CY7C1361C-133AXI Datasheet - Page 8

• Manufacturer Part Number: CY7C1361C-133AXI
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1361C-133AXI

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Definitions
Document Number: 38-05541 Rev. *J
A
BW
BW
GW
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
BWE
ZZ
DQ
DQP
Note
3. CE
0
, A
1
2
3
s
A
C
[3]
,BW
X
,BW
1
Name
, A
3
is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
B
D
asynchronous
asynchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
clock
I/O-
I/O-
I/O
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
active. A
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tristated, and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Advance input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized.
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQ
condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
During write sequences, DQP
[1:0]
1
[1:0]
[1:0]
is sampled only when a new external address is loaded.
feed the 2-bit counter.
are also loaded into the burst counter. When ADSP and ADSC are both
are also loaded into the burst counter. When ADSP and ADSC are both
1
2
1
and CE
and CE
and CE
3
3
2
[3]
[3]
X
to select/deselect the device. CE
is controlled by BW
to select/deselect the device. CE
to select/deselect the device. ADSP is ignored if CE
Description
s
and DQP
X
CY7C1361C/CY7C1363C
correspondingly.
X
1
, CE
are placed in a tristate
2
1
, and CE
3
is deasserted HIGH.
2
is sampled only when
is sampled only when
3
[3]
are sampled
X
and BWE).
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