CY7C136-25JXC Cypress Semiconductor Corp, CY7C136-25JXC Datasheet - Page 8

• Manufacturer Part Number: CY7C136-25JXC
• Description: IC SRAM 16KBIT 25NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C136-25JXC

• Memory Size: 16K (2K x 8)
• Package / Case: 52-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 25 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 170 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Memory Configuration: 2K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: LCC
• No. Of Pins: 52
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2038-5; CY7C136-25JXC

Switching Waveforms
Document #: 38-06031 Rev. *G
Note
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
ADDRESS
ADDRESS
ADDRESS
and for data to be placed on the bus for the required t
DATA
BUSY
DOUT
D
R/W
R/W
OUT
D
OE
CE
IN
INR
R
L
R
L
L
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
t
HZOE
(continued)
t
SA
t
PS
SD
.
t
BLA
t
SCE
ADDRESS MATCH
t
AW
t
WC
t
RC
t
PWE
HIGH IMPEDANCE
ADDRESS MATCH
t
PWE
DATA VALID
t
SD
PWE
t
WDD
VALID
or t
CY7C136A, CY7C142, CY7C146
HZWE
+ t
t
SD
DDD
t
to allow the data I/O pins to enter high impedance
BHA
t
HD
t
HA
[12, 20]
CY7C132, CY7C136
t
BDD
VALID
Page 8 of 15
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