CY7C1231H-133AXC Cypress Semiconductor Corp, CY7C1231H-133AXC Datasheet
CY7C1231H-133AXC
Specifications of CY7C1231H-133AXC
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CY7C1231H-133AXC Summary of contents
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... The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231H is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle ...
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... Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Pin Configuration DDQ DDQ BYTE DDQ DQP DDQ Document #: 001-00207 Rev. *B 133 MHz 6.5 225 40 100-pin TQFP Pinout CY7C1231H CY7C1231H Unit DDQ DQP DDQ BYTE DDQ DDQ Page ...
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... The outputs are automatically tri-stated during [A:B] is controlled by BW correspondingly. [A: left floating selects interleaved burst sequence. CY7C1231H . During write s Page ...
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... OE. Burst Write Accesses The CY7C1231H has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... None None External Next External Next External Next None Next Current None data when OE is active. [A:B] CY7C1231H Second Third Address Address A1 Min. Max CYC 2t CYC 2t CYC 0 OE CEN CLK L-> L-> L-> L-> L->H Data Out ( L->H Data Out (Q) ...
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... MHz DD ≥ V ≤ 0.3V, V – 0. inputs static /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1231H Ambient Temperature ( 0°C to +70°C 3.3V – 5%/+10% -40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... EIA/JESD51 R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND SCOPE ( 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND SCOPE (b) CY7C1231H 100 TQFP Max 3. 2.5V 5 100 TQFP Package 30.32 6.85 ALL INPUT PULSES V DDQ 90% 10% GND ≤ (c) ...
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... V = 2.5V. DDQ is the time that the power needs to be supplied above V POWER is less than t and t is less than t OELZ CHZ CLZ CY7C1231H -133 Min. Max. 1 7.5 2.5 2.5 6.5 2.0 0 3.5 3 ...
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... A3 t CDV t DOH t CLZ D(A2) Q(A3) D(A2+1) t OEHZ BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1231H OEV t CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ BURST WRITE READ WRITE READ D(A5) Q(A6) ...
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... I/Os are in tri-state when exiting ZZ sleep mode. Document #: 001-00207 Rev Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED High-Z DON’T CARE CY7C1231H CHZ D(A4) Q(A5) t DOH NOP READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only ...
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... Please contact your local sales representative or visit Speed Package (MHz) Ordering Code Diagram 133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free Package Diagram 100 0.08 MIN. 0° ...
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... Document History Page Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-00207 REV. ECN NO. Issue Date ** 347377 See ECN *A 428408 See ECN *B 459347 See ECN Document #: 001-00207 Rev. *B Orig. of Change Description of Change PCI New Data Sheet NXR Converted from Preliminary to Final ...