CY62147EV30LL-45BVXI Cypress Semiconductor Corp, CY62147EV30LL-45BVXI Datasheet - Page 8

• Manufacturer Part Number: CY62147EV30LL-45BVXI
• Description: IC SRAM 4MBIT 45NS 48VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62147EV30LL-45BVXI

• Memory Size: 4M (256K x 16)
• Package / Case: 48-VFBGA
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Memory Configuration: 256K X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 18b
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Supply Current: 20mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2072; CY62147EV30LL-45BVXI

Switching Waveforms
Document Number: 38-05440 Rev. *J
Notes
26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
27. The internal write time of the memory is defined by the overlap of WE, CE = V
28. Data I/O is high impedance if OE = V
29. If CE goes HIGH simultaneously with WE = V
30. During this period, the I/Os are in output state. Do not apply input signals.
ADDRESS
ADDRESS
and CE
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
BHE/BLE
BHE/BLE
DATA I/O
DATA I/O
2
WE
WE
OE
OE
CE
CE
such that when CE
NOTE 30
NOTE 30
1
is LOW and CE
(continued)
IH
.
t
HZOE
t
SA
t
HZOE
Figure 8. Write Cycle No. 1: WE Controlled
Figure 9. Write Cycle No. 2: CE Controlled
2
IH
is HIGH, CE is LOW. For all other cases CE is HIGH.
, the output remains in a high impedance state.
t
SA
t
AW
t
AW
t
t
SCE
WC
t
IL
WC
, BHE, BLE, or both = V
t
BW
t
BW
DATA
t
t
PWE
SD
DATA
t
t
PWE
SD
t
IN
SCE
IN
IL
[26, 27, 28, 29]
[26, 27, 28, 29]
. All signals must be active to initiate a write and any
t
HD
t
CY62147EV30 MoBL
HA
t
HA
t
HD
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