M29W400DT70ZE6E NUMONYX, M29W400DT70ZE6E Datasheet

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... Automotive Device Grade 3 – Temperature: –40 to 125 °C – Automotive grade certified April 2009 4 Mbit (512 256 Kb x 16, boot block) 1. These packages are no more in mass production. Rev 8 M29W400DT M29W400DB 3 V supply Flash memory (1) SO44 (M) TSOP48 ( FBGA (1) TFBGA48 (ZA FBGA TFBGA48 (ZE www.numonyx.com 1/48 1 ...

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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 Chip Erase ...

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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... The memory is offered in SO44, TSOP48 ( mm), TFBGA48 0.8 mm pitch ( and mm) packages. The memory is supplied with all the bits erased (set to ’1’). In order to meet environmental requirements, Numonyx offers the M29W400D in RoHS packages, which are Lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...

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Figure 1. Logic diagram A0-A17 Table 1. Signal names Signal name A0-A17 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A–1 Data input/output or Address input E Chip Enable G Output Enable W Write Enable RP ...

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Figure 2. SO connections Not connected. 8/ A17 A10 A11 A12 A3 8 ...

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Figure 3. TSOP connections A15 A14 A13 A12 A11 A10 A17 Not connected A16 BYTE V SS DQ15A–1 ...

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Figure 4. TFBGA connections (top view through package Not connected. 10/ A17 ...

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Figure 5. Block addresses (x 8) M29W400DT Top boot block addresses (x 8) 7FFFFh 16 Kbyte 7C000h 7BFFFh 8 Kbyte 7A000h 79FFFh 8 Kbyte 78000h 77FFFh 32 Kbyte 70000h 6FFFFh 64 Kbyte 60000h 1FFFFh 64 Kbyte 10000h 0FFFFh 64 Kbyte ...

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Figure 6. Block addresses (x 16) M29W400DT Top boot block addresses (x 16) 3FFFFh 8 Kword 3E000h 3DFFFh 4 Kword 3D000h 3CFFFh 4 Kword 3C000h 3BFFFh 16 Kword 38000h 37FFFh 32 Kword 30000h 0FFFFh 32 Kword 08000h 07FFFh 32 Kword ...

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... Figure 1: Logic this device. 2.1 Address inputs (A0-A17) The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation ...

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... PHPHH 2.9 Ready/Busy output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance ...

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... This prevents Bus Write operations from accidentally damaging the data LKO during power-up, power-down and power surges. If the Program/Erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 μF capacitor should be connected between the V ground pin to decouple the current surges from the power supply ...

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... Enable are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the command interface. A valid Bus Read operation involves setting the desired address on the Address inputs, applying a Low signal, V Enable High, V ...

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... They require V applied to some pins. 3.7 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and 3, Bus operations. ...

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Table 3. Bus operations, BYTE = V Operation Bus Read Bus Write Output Disable Standby Read manufacturer code Read device code 18/48 IH Address inputs A0-A17 V V ...

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... From the Auto Select mode the manufacturer code can be read using a Bus Read operation with and manufacturer code for Numonyx is 0020h. The device code can be read using a Bus Read operation with other address bits may be set to either V 00EEh and for the M29W400DB is 00EFh. ...

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... Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory ...

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... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks ...

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... Program/Erase controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued ...

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Table 5. Commands, 16-bit mode, BYTE = V Command 1st Addr 1 X Read/Reset 3 555 Auto Select 3 555 Program 4 555 Unlock Bypass 3 555 Unlock Bypass 2 X Program Unlock Bypass 2 X Reset Chip Erase 6 ...

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... DQ7, not its complement. During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling bit will change from a ’ ...

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... Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’ ...

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Table 7. Status Register bits Operation Block Erase before timeout Block Erase Erase Suspend Erase Error 1. Unspecified data bits should be ignored. Figure 7. Data polling flowchart 26/48 (1) (continued) Address DQ7 DQ6 Erasing block 0 Toggle Non-erasing 0 ...

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Figure 8. Data toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C 27/48 ...

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... V Identification voltage ID 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn- assermbly), the Numonyx RoHS specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Minimum voltage may undershoot to –2 V during transition and for less than 20 ns during transitions. 3. Maximum voltage may overshoot to V ...

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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...

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Table 10. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 11. DC characteristics Symbol I Input Leakage current LI I Output Leakage current LO I Supply current (Read) CC1 I ...

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Table 12. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ( Chip Enable Low to Output Transition ELQX Chip ...

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Figure 12. Write AC waveforms, Write Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 13. Write AC characteristics, Write Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t ...

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Figure 13. Write AC waveforms, Chip Enable controlled A0-A17/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 14. Write AC characteristics, Chip Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...

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Figure 14. Reset/Block Temporary Unprotect AC waveforms tPLPX RP Table 15. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL RH Low, Output Enable ...

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Package mechanical Figure 15. SO44 - 44 lead plastic small outline, 525 mils body width, package outline b 1. Drawing is not to scale. Table 16. SO44 – 44 lead plastic small outline, 525 mils body width, package mechanical ...

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Figure 16. TSOP48 – 48 lead plastic thin small outline mm, package outline DIE 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead plastic thin small outline mm, ...

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Figure 17. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline FD FE BALL "A1" Drawing is not to scale. Table 18. TFBGA48 mm, ...

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Figure 18. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline 1. Drawing is not to scale. Table 19. TFBGA48 mm active ball array, 0.80 ...

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... The part is qualfied and tested according to the AEC-Q100 rev. G specifications. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. M29W400DT (2) (– ...

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Appendix A Block address table Table 21. Top boot block addresses M29W400DT # Size (Kbytes Table 22. Bottom ...

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... Unlike the command interface of the Program/Erase controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on Numonyx parts. Care should be taken when changing drivers for one part to work on another. ...

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Table 23. Programmer technique bus operations, BYTE = V Operation Block Protect Chip Unprotect Block Protection Verify Block Unprotection Verify 42/48 Address inputs A0-A17 A12-A17 block address pulse ...

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Figure 19. Programmer equipment block protect flowchart ADDRESS = BLOCK ADDRESS START Wait 4 µ Wait 100 µs W ...

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Figure 20. Programmer equipment chip unprotect flowchart NO 44/48 START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4 µ Wait ...

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Figure 21. In-system equipment block protect flowchart WRITE 60h ADDRESS = BLOCK ADDRESS WRITE 60h ADDRESS = BLOCK ADDRESS ...

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Figure 22. In-system equipment chip unprotect flowchart 46/48 START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...

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... RoHS text added in Section 1: 5 Updated options E and F in Small text changes. 6 Applied Numonyx branding. Added Automotive Grade 3 part information to cover page and part 7 ordering information. Revised BYTE signal name from “output” to “input” in names; Revised Chip Erase signal value (maximum) in ...

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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...