M95512-RDW6TP STMicroelectronics, M95512-RDW6TP Datasheet - Page 45

• Manufacturer Part Number: M95512-RDW6TP
• Description: IC EEPROM 512KBIT 2MHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M95512-RDW6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 512K (64K x 8)
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 64 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6358-2; M95512-RDW6TP

M95512-DR, M95512-W, M95512-R
13
Revision history
Table 25.
05-Dec-2003
13-Feb-2002
02-Apr-2004
03-Jan-2005
30-Jun-2005
Jan-1999
Date
Document revision history
Revision
1.0
2.0
3.0
4.0
5.0
6.0
Document written
Document reformatted using the new template
Voltage range -S added, and -R removed
Instruction Sequence illustrations updated
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range
Table of contents, and Pb-free options added. V
0.45V. Voltage range -R added, and -S removed
Old versions of document completely replaced by one rewritten from
M95256
AC and DC characteristics tables updated with the performance data of
the new device identified with the process letter “A”.
Table 1., Product List
information clarified. t
t
M95512 part number with 4.5V to 5.5V operating voltage range removed
(related tables removed). Document status changed to Preliminary Data.
Updated
Figure 21: Hold
Array Addresses modified in
Operating Temperature value added in
ratings. Supply Current (I
characteristics (current M95512-W
Table 19: AC characteristics (current and new M95512-R and M95512-DR
products). Document status changed to Datasheet.
CLHH
, respectively.
Doc ID 11124 Rev 14
Figure 4: Bus master and memory devices on the SPI bus
timing.
HHQX
added. AEC-Q100-002 compliance. Device Grade
Power On Reset
CC
, t
) value modified for 10 MHz in
CHHL
Table 2: Write-protected block
Changes
and t
products). All values modified in
CHHH
Table 7: Absolute maximum
information clarified. Protected
corrected to t
IL
(min) improved to -
Revision history
HHQV
Table 14: DC
size. Ambient
, t
CLHL
and
45/48
and