M24C02-RDW6T STMicroelectronics, M24C02-RDW6T Datasheet - Page 13
![IC EEPROM 2KBIT 400KHZ 8TSSOP](/photos/5/43/54342/497-8-tssop_sml.jpg)
M24C02-RDW6T
Manufacturer Part Number
M24C02-RDW6T
Description
IC EEPROM 2KBIT 400KHZ 8TSSOP
Manufacturer
STMicroelectronics
Datasheet
1.M24C01-WMN6TP.pdf
(39 pages)
Specifications of M24C02-RDW6T
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1605-2
M24C02-RDW6TP
M24C02-RDW6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M24C02-RDW6T
Manufacturer:
SMC
Quantity:
297
Part Number:
M24C02-RDW6T
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M24C02-RDW6TP
Manufacturer:
STMicroelectronics
Quantity:
476
Part Number:
M24C02-RDW6TP
Manufacturer:
ST
Quantity:
20 000
M24C16, M24C08, M24C04, M24C02, M24C01
3.6
3.6.1
Figure 7.
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte’s Ack bit (in
the “10
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High (during
the period from the Start condition until the end of the address byte), the device replies to
the data byte with NoAck, as shown in
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
Write mode sequences with WC = 1 (data write inhibited)
NO ACK
Dev select
Dev select
Data in N
Doc ID 5067 Rev 16
R/W
R/W
ACK
ACK
NO ACK
Byte address
Byte address
Figure
7, and the location is not modified. If, instead,
ACK
ACK
Data in 1
Data in
NO ACK
NO ACK
Figure
Data in 2
8, and waits for an
NO ACK
Device operation
Data in 3
AI02803d
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