CAT1027WI-45-G ON Semiconductor, CAT1027WI-45-G Datasheet - Page 13

• Manufacturer Part Number: CAT1027WI-45-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1027WI-45-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

Immediate/Current Address Read
The CAT1026 and CAT1027 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1026and CAT1027 receive its
slave address information (with the R/W ¯ ¯ bit set to
one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not
send an acknowledge, but will generate a STOP
condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave
address again, this time with the R/W ¯ ¯ bit set to one.
The CAT1026 and CAT1027 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Figure 11. Selective Read Timing
Figure 12. Sequential Read Timing
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
SDA LINE
MASTER
ADDRESS
SLAVE
S
S
T
A
R
T
A
C
K
ADDRESS
SLAVE
DATA n
A
C
K
ADDRESS (n)
A
C
K
BYTE
DATA n+1
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Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1026 and CAT1027 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1026 and CAT1027 address bits so that the entire
memory array can be read during one operation.
A
C
K
R
S
T
A
T
S
C
A
K
ADDRESS
SLAVE
DATA n+2
A
C
K
A
C
K
DATA n
CAT1026, CAT1027
DATA n+x
N
O
C
A
K
P
S
O
P
T
Doc. No. MD-3010 Rev. P
N
O
C
A
K
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O
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