M24C08-WMN6TP STMicroelectronics, M24C08-WMN6TP Datasheet - Page 17
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M24C08-WMN6TP
Manufacturer Part Number
M24C08-WMN6TP
Description
IC EEPROM 8KBIT 400KHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M24C01-WMN6TP.pdf
(39 pages)
Specifications of M24C08-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
8K (1K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
8Kb
Interface Type
Serial (I2C)
Organization
1Kx8
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
SOIC
Operating Temp Range
-40C to 85C
Supply Current
2mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Maximum Clock Frequency
0.4 MHz
Access Time
900 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8554-2
M24C08-WMN6TP
Q2040217
M24C08-WMN6TP
Q2040217
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M24C08-WMN6TP
Manufacturer:
STM
Quantity:
20 000
Company:
Part Number:
M24C08-WMN6TPGCB
Manufacturer:
ST
Quantity:
2 293
M24C16, M24C08, M24C04, M24C02, M24C01
3.7.2
3.7.3
3.7.4
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9
time, the device terminates the data transfer and switches to its Standby mode.
10, without acknowledging the byte.
th
bit time. If the bus master does not drive Serial Data (SDA) Low during this
Figure
10.
Doc ID 5067 Rev 16
Device operation
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