CY7C028V-20ACT Cypress Semiconductor, CY7C028V-20ACT Datasheet
CY7C028V-20ACT
Specifications of CY7C028V-20ACT
Related parts for CY7C028V-20ACT
CY7C028V-20ACT Summary of contents
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... Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027V/027AV ■ 64K x 16 organization (CY7C028V) ■ 32K x 18 organization (CY7C037AV) ■ 64K x 18 organization (CY7C038V) ■ 0.35 micron Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ ...
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... CY7C037AV/038V Timing ................................................................................ 9 Switching Waveforms .................................................... 10 Ordering Information ...................................................... 17 32K x16 3.3 V Asynchronous Dual-Port SRAM ........ 17 64K x16 3.3 V Asynchronous Dual-Port SRAM ........ 17 32K x18 3.3 V Asynchronous Dual-Port SRAM ........ 17 64K x18 3.3 V Asynchronous Dual-Port SRAM ........ 17 Ordering Code Definition ........................................... 18 Package Diagram ............................................................ 19 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ...
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... Note 6. This pin is NC for CY7C027V/027AV. Document #: 38-06078 Rev. *E Figure 1. 100-Pin TQFP (Top View CY7C028V (64K x 16) CY7C027V/027AV (32K x 16 CY7C027V/027AV/028V CY7C037AV/038V ...
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Pin Configurations (continued) 100 99 98 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [7] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND 16 I/O17L ...
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... CY7C027V/027AV/037AV, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...
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Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port ...
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... Input capacitance IN C Output capacitance OUT Notes 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C028V and CY7C038V, CY7C027V/027AV only. 10 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...
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590 OUTPUT 435 (a) Normal Load (Load 1) Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read cycle time RC t Address to data valid ...
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Switching Characteristics Over the Operating Range Parameter Description t Data hold from write end HD [17, 18] t R/W LOW to High Z HZWE [17, 18] t R/W HIGH to Low Z LZWE [21] t Write pulse to data delay ...
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Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...
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Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [32,33 R/W ...
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Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...
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Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41. CE ...
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Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing ...
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... Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE 7FFE (FFFE for CY7C028V/38V R/W R INT L [44] ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes 45. A and A ,FFFF/FFFE for the CY7C028V/038V. 0L–15L 0R–15R 46. If BUSY =L, then no change. R 47. If BUSY =L, then no change. ...
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... CY7C027V-20AXC 25 CY7C027V-25AC CY7C027V-25AXC CY7C027AV-25AXI 64K x16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AXC CY7C028V-15AXI 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C037AV-20AXC 64K x18 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C038V-20AXI Document #: 38-06078 Rev. *E ...
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... Ordering Code Definition Document #: 38-06078 Rev CY7C027V/027AV/028V CY7C037AV/038V Operating Range C = Com m ercial I = Industrial free (RoHS Com pliant) Package: A=TQFP Speed Grade : 15ns/20ns/25ns X = V/AV : 3.3 V Depth: 7=32K or 8=64K W idth: 02=x16 or 03=x18 7C = Dual Port SRAM Com pany ID Cypress Page ...
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Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *E CY7C027V/027AV/028V CY7C037AV/038V 51-85048 *E Page ...
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... Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SRAM static random access memory TQFP thin quad plastic flatpack Document #: 38-06078 Rev. *E CY7C027V/027AV/028V CY7C037AV/038V Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius MHz mega hertz µA microamperes mA milliamperes mV millivolts ...
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... Document History Page Document Title: CY7C027V/027AV/CY7C028V/037AV/038V 3.3 V 32K/64K X 16/18 DUAL PORT STATIC RAM Document Number: 38-06078 Orig. of Rev. ECN No. Change ** 237626 YDT *A 259110 JHX *B 2623540 VKN/PYRS *C 2897217 RAME *D 3093542 ADMU *E 3403652 ADMU Document #: 38-06078 Rev. *E Submission Date 6/30/04 Converted data sheet from old spec 38-00670 to conform with new data sheet ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...