CAT1024ZI45 ON Semiconductor, CAT1024ZI45 Datasheet - Page 6

• Manufacturer Part Number: CAT1024ZI45
• Description: Supervisory Circuits 2K bit 4.5V Ind Temp
• Manufacturer: ON Semiconductor

Specifications of CAT1024ZI45

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 5
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 4.5 V to 4.75 V
• Overvoltage Threshold: 4.75 V
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 200 mS
• Supply Voltage - Max: 5 V, 3.3 V, 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MSOP-8
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage V
3. Power−Down, Input Reference Voltage V
4. V
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to V
I
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
LTH
Table 9. RESET CIRCUIT AC CHARACTERISTICS
Table 10. POWER−UP TIMING
Table 11. AC TEST CONDITIONS
Table 12. RELIABILITY CHARACTERISTICS
N
V
T
PUR
END
ZAP
CC
MR Glitch
DR
(Notes 5 & 7)
Symbol
Symbol
Symbol
t
t
GLITCH
PURST
t
t
t
t
t
Glitch Reference Voltage = V
MRW
MRD
PUW
(Note 5)
and t
RDP
PUR
(Note 5)
(Note 5)
PUW
are the delays required from the time V
Parameter
Power−Up Reset Timeout
V
V
Manual Reset Glitch Immunity
MR Pulse Width
MR Input to RESET Output Delay
Power−Up to Read Operation
Power−Up to Write Operation
Endurance
Data Retention
ESD Susceptibility
Latch−Up
TH
CC
to RESET output Delay
Glitch Reject Pulse Width
Parameter
THmin
(Notes 5 and 6)
Parameter
Parameter
CC
; Based on characterization data
= V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
Current Source: I
CC
http://onsemi.com
Reference Test Method
is stable until the specified memory operation can be initiated.
JEDEC Standard 17
0.2 x V
0.3 x V
Test Conditions
6
0.5 x V
CC
CC
OL
10 ns
Test Conditions
Test Conditions
to 0.8 x V
Notes 4 and 5
, 0.7 x V
= 3 mA; C
CC
Note 2
Note 3
Note 1
Note 1
Note 1
CC
CC
L
= 100 pF
1,000,000
2000
Min
100
100
CC
Min
Min
130
5
+ 1 V.
Typ
200
Typ
Max
Max
Max
270
100
270
270
30
5
1
Cycles/Byte
Units
Years
Volts
mA
Units
Units
ms
ms
ms
ns
ns
ms
ms
ms