MAX3292EPD Maxim Integrated, MAX3292EPD Datasheet - Page 7

• Manufacturer Part Number: MAX3292EPD
• Description: RS-422/RS-485 Interface IC
• Manufacturer: Maxim Integrated

Specifications of MAX3292EPD

• Data Rate: 10 Mbps
• Operating Supply Voltage: 5 V
• Supply Current: 3 mA
• Operating Temperature Range: 0 C to + 70 C
• Number Of Drivers: 1
• Number Of Receivers: 1
• Product: RS-422/RS-485 Combination

Figure 1. Driver DC Test Load
MAX3291
6, 8, 13
—
10
11
12
—
14
1
2
3
4
5
7
9
for High-Speed, Long-Distance Communication
RS-485/RS-422 Transceivers with Preemphasis
PIN
MAX3292
Y
Z
6, 7
10
11
12
13
14
—
1
2
3
4
5
8
9
_______________________________________________________________________________________
V
V
OD
ODP
NAME
V
PSET
GND
N.C.
PEE
V
RO
DE
RE
CCD
DI
Y
Z
B
A
CC
R
R
V
OC
Preemphasis Enable Input. To enable preemphasis, leave PEE unconnected, connect to
V
low.
Preemphasis Set Input. Sets the preemphasis interval. Connect a resistor (R
lel with a capacitor (C
Operating Circuit .
Receiver Output. When RE is low and if A - B ≥ 200mV, RO is high; if A - B ≤ -200mV, RO
is low.
Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is
high. Drive RE high and DE low to enter low-power shutdown mode.
Driver Output Enable. Drive DE high to enable the driver outputs. These outputs are high
impedance when DE is low. Drive RE high and DE low to enter low-power shutdown mode.
Driver Input. With DE high, a low on DI forces the noninverting output low and the inverting
output high. Similarly, a high on DI forces the noninverting output high and the inverting
output low.
No Connection. Not internally connected.
Ground
Noninverting Driver Output
Inverting Driver Output
Inverting Receiver Input
Noninverting Receiver Input
Connect to V
Positive Supply: +4.75V ≤ V
CC
, or drive high. To enable strong-level-drive only mode, connect PEE to GND or drive
CC
PSET
) from PSET to V
CC
Figure 2. Driver or Receiver Enable/Disable Timing Test Load
≤ +5.25V
UNDER TEST
OUTPUT
FUNCTION
CC
to set the preemphasis interval. See Typical
C
L
R
L
Pin Description
S1
S2
PSET
) in paral-
V
CC
7