AS7C31024B-12TJCN Alliance Memory, AS7C31024B-12TJCN Datasheet - Page 2
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AS7C31024B-12TJCN
Manufacturer Part Number
AS7C31024B-12TJCN
Description
SRAM 1M, 3.3V, 12ns, FAST 128K x 8 Asynch SRAM
Manufacturer
Alliance Memory
Datasheet
1.AS7C31024B-15TJCN.pdf
(9 pages)
Specifications of AS7C31024B-12TJCN
Rohs
yes
Memory Size
1 Mbit
Organization
128 K x 8
Access Time
12 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
SOJ-32
Interface
Parallel
Maximum Clock Frequency
83 MHz
Factory Pack Quantity
22
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AS7C31024B-12TJCN
Manufacturer:
ON
Quantity:
101
Functional description
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words
x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I
static, then full standby power is reached (I
standby conditions.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is
written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = don’t care, L = low, H = high
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
3/24/04, v.1.2
CE1
H
X
L
L
L
CC
relative to GND
CE2
X
H
H
H
L
Parameter
CC
applied
WE
AA
X
X
H
H
L
, t
SB1
RC
, t
). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full
WC
Alliance Semiconductor
) of 10/12/15/20 ns with output enable access times (t
OE
X
X
H
X
L
Symbol
I
T
T
V
V
OUT
P
bias
stg
D
t1
t2
®
High Z
High Z
High Z
D
Data
D
OUT
IN
–0.50
-0.50
Min
–65
–55
–
–
OE
V
Output disable (I
) of 5, 6, 7, 8 ns are ideal for
CC
Standby (I
Standby (I
+150
+125
Max
+5.0
1.0
20
+0.50
Write (
Read (I
SB
Mode
AS7C31024B
power. If the bus is
SB
SB
ICC
CC
, I
, I
P. 2 of 9
)
)
SB1
SB1
CC
Unit
mA
)
)
°C
°C
W
V
V
)