MP6400DJ-01-LF-Z Monolithic Power Systems (MPS), MP6400DJ-01-LF-Z Datasheet - Page 8

• Manufacturer Part Number: MP6400DJ-01-LF-Z
• Description: Supervisory Circuits Low Quiescent Delay Supv Circuit
• Manufacturer: Monolithic Power Systems (MPS)

Specifications of MP6400DJ-01-LF-Z

• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 0.4 V
• Overvoltage Threshold: Adjustable
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 380 ms
• Supply Voltage - Max: 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOT23-6
• Maximum Power Dissipation: 570 mW
• Power Fail Detection: Yes
• Supply Current (typ): 1.6 uA
• Supply Voltage - Min: 1.8 V

APPLICATION INFORMATION
Reset Output Function
The MP6400
to the
in Figure 3. When
up resistor must be connected to hold this signal
high. The voltage of reset signal is allowed to be
higher than V
pulling up from supply line. If the voltage is below
0.8V,
can be ignored generally because that most
microprocessors do not function at this state.
When both SENSE and
threshold voltage,
Once either of the two drops below their
threshold,
From the point that
SENSE is above V
hysteresis),
after a reset delay time. The reset delay time is
programmable by C
impedance of
should be bigger than 10kΩ.
Monitor a Voltage
The SENSE input pin is connected to the
monitored system voltage directly or through a
resistor network (on MP6400DJ-01). When the
voltage on the pin is below V
A threshold hysteresis will prevent the chip from
responding perturbation on SENSE pin. A 1nF to
10nF bypass capacitor should be put on this pin
to increase its immunity to noise. A typical
application of the MP6400DJ-01 is shown in
Figure 4. Two external resistors form a voltage
divider from monitored voltage to GND. Its tap
MP6400 Rev. 0.91
12/16/2009
Figure 3—Typical Application of MP6400 with
V
0.1uF
CC
R E S E T
R E S E T
1nF
R2
R1
R E S E T
R E S E T
input of a microprocessor, as shown
output is undefined. This condition
R E S E T
MP6400 – LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
CC
Microprocessor
R E S E T
MR
SENSE
will be asserted.
(up to 6V) through a resistor
GND C
will be driven to a logic high
R E S E T
output is typically connected
VCC
R E S E T
DELAY
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
M R
RESET
IT
pin, the pull up resistor
DELAY
is again logic high and
output holds logic high.
C
+ V
M R
DELAY
is not asserted, a pull
pin. Due to the finite
are higher than their
IT
HYS
47pF
,
100k
R E S E T
Microprocessor
Microcontroller
(the threshold
RESET
is asserted.
© 2009 MPS. All Rights Reserved.
DSP
GND
www.MonolithicPower.com
connects to the SENSE pin. The circuit can be
used to monitor any voltage higher than 0.4V.
Monitor Multiple System Voltages
logic signal to control the
logic low (0.25V
both SENSE and
delay time. The
through a 90kΩ resistor so this pin can float. See
how multiple system voltages are monitored by
there will be an additional current through internal
90kΩ pull up resistor. A logic-level FET can be
used to minimize the leakage, as shown in Figure
6.
Figure 5— MP6400 Family Monitoring Multiple
The manual reset (
R E S E T
M R
Figure 4—MP6400DJ-01 Monitoring a User-
MP6400DJ-12
1.2V
in Figure 5. If the signal on
C
1nF
SENSE
DELAY
will be driven to a logic high after a reset
GND
R2
R1
RESET
V
VCC
SEN
System Voltages
Defined Voltage
CC
SENSE
M R
MP6400DJ-01
),
M R
3.3V
MP6400DJ-33
is internally connected to V
C
MR
SENSE VCC
R E S E T
DELAY
GND
VCC
are above their thresholds,
M R
GND
RESET
) can introduce another
RESET
will be asserted. After
R E S E T
M R
. When
isn’t up to V
V
IT
RESET
= (1+
V
I/O
DSP
GND
V
R1
R2
M R
OUT
V
CORE
)
0.4
is a
CC
CC
8
,