MAX5168NCCM Maxim Integrated, MAX5168NCCM Datasheet - Page 12

• Manufacturer Part Number: MAX5168NCCM
• Description: Sample & Hold Amplifiers
• Manufacturer: Maxim Integrated
• Series: MAX5168r

Specifications of MAX5168NCCM

• Number Of Channels: 32
• Acquisition Time: 4 us
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Dual Supply Voltage: - 4.75 V, + 9.5 V

The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information ). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
microcontroller I/O pins required. During power-down,
this output will retain its digital state prior to shutdown.
Low-Power, Serial, 12-Bit DACs with
Force/Sense Voltage Output
Figure 4. Serial-Interface Timing Diagram
Figure 5. Detailed Serial-Interface Timing Diagram
12
User-Programmable Logic Output (UPO)
______________________________________________________________________________________
DOUT
SCLK
SCLK
DIN
CS
DIN
CS
Serial-Data Output (DOUT)
C2
1
t
CSO
C1
C0
D9
t
DS
D8
t
CSS
D7
D6
t
D5
D01
8
t
CH
D4
t
CSH
9
t
When CLR is pulled low, UPO will reset to its pro-
grammed default state. See Table 1 for specific com-
mands to control the UPO.
The MAX5175/MAX5177 offers a clear pin (CLR) which
resets the output voltage. If RST = DGND, then CLR
resets the output voltage to the minimum voltage (0 if
no offset is introduced). If RST = V
the output voltage to midscale. In either case, CLR will
reset UPO to its programmed default state.
CP
D3
t
D02
t
D2
CL
D1
D0
t
S2
CS1
t
CSW
t
DH
S1
Reset (RS) and Clear (
S0
16
COMMAND
EXECUTED
DD
, then CLR resets
C C L L R R )