MCIMX6D4AVT10ACR Freescale Semiconductor, MCIMX6D4AVT10ACR Datasheet - Page 71
MCIMX6D4AVT10ACR
Manufacturer Part Number
MCIMX6D4AVT10ACR
Description
Processors - Application Specialized i.MX6D
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6D4AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Figure 38
Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200MB/s.
GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,
which can be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX
6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value of this register is equal
to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and
cannot be ignored, the delay value should be made larger to compensate the board delay.
Freescale Semiconductor
1
2
NF18 NAND_CEx_B access time
NF19 NAND_CEx_B hold time
NF20 Command/address NAND_DATAxx setup time
NF21 Command/address NAND_DATAxx hold time
NF22 clock period
NF23 preamble delay
NF24 postamble delay
NF25 NAND_CLE and NAND_ALE setup time
NF26 NAND_CLE and NAND_ALE hold time
NF27 NAND_CLK to first NAND_DQS latching transition
NF28 Data write setup
NF29 Data write hold
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
ID
The GPMI source synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Table 50. Source Synchronous Mode Timing Parameters
Parameter
Figure 38. NAND_DQS/NAND_DQ Read Valid Window
Symbol
tDQSS
tDQSQ
tPOST
tCALS
tCALH
tQHS
tCAS
tCAH
tPRE
tCE
tCH
tCK
tDS
tDH
POST_DELAY T - 0.78 [see
PRE_DELAY T - 0.29 [see
CE_DELAY T - 0.79 [see
T = GPMI Clock Cycle
0.5 tCK - 0.63 [see
Min
—
—
0.25 tCK - 0.35
0.25 tCK - 0.85
0.5 tCK - 0.05
0.5 tCK - 1.23
0.5 tCK - 0.86
0.5 tCK - 0.37
T - 0.41 [see
Timing
—
1
Electrical Characteristics
2
]
Max
2.06
1.95
2
]
2
2
]
2
]
]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
71
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