MCIMX503CVK8B Freescale Semiconductor, MCIMX503CVK8B Datasheet - Page 56
MCIMX503CVK8B
Manufacturer Part Number
MCIMX503CVK8B
Description
Processors - Application Specialized CODEX 13MM REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX503EVM8B.pdf
(135 pages)
Specifications of MCIMX503CVK8B
Core
ARM Cortex A8
Processor Series
i.MX50
Data Bus Width
32 bit
Operating Supply Voltage
0.75 V to 1.275 V
Memory Type
L1/L2 Cache, ROM, SRAM
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Electrical Characteristics
4.6.5.3
4.6.5.3.1
56
1
GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY,
HW_GPMI_TIMING_PREAMBLE_DELAY, and HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these
registers’ setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each.
NF24
NF25
NF26
NF27
ID
postamble delay
CLE and ALE setup time
CLE and ALE hold time
Data input to first DQS
latching transition
Samsung Toggle Mode AC Timing
Command and Address Timing
Samsung Toggle Mode command and address timing is the same as ONFI
1.0 compatible Async mode AC timing. Please refer to the above chapter for
details.
Table 40. Source Synchronous Mode Timing Parameters
Parameter
i.MX50 Applications Processors for Consumer Products, Rev. 4
Symbol
t
t
t
t
POST
DQSS
CALS
CALH
NOTE
POST_DELAY*t
0.5*t
0.5*t
Min.
t
CK
CK
CK
T = GPMI Clock Cycle
CK
Timing
1
(continued)
Max.
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
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