MCIMX6D6AVT10ACR Freescale Semiconductor, MCIMX6D6AVT10ACR Datasheet - Page 60
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MCIMX6D6AVT10ACR
Manufacturer Part Number
MCIMX6D6AVT10ACR
Description
Processors - Application Specialized i.MX6D
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6D6AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Electrical Characteristics
4.9.4
4.9.4.1
Figure 24
in
60
DDR1
DDR2
In this table:
— CSA means WCSA when write operation or RCSA when read operation
— CSN means WCSN when write operation or RCSN when read operation
— t means axi_clk cycle time
— ADVN means WADVN when write operation or RADVN when read operation
— ADVA means WADVA when write operation or RADVA when read operation
Table
ID
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDCKEx
DRAM_RAS_B
DRAM_SDWE_B
DRAM_ADDRxx
DRAM_CSx_B
DRAM_ODTx/
DRAM_CAS_B
43.
DRAM_SDCLKx_P clock high-level width
DRAM_SDCLKx_P clock low-level width
shows the DDR3/DDR3L basic timing diagram. The timing parameters for this diagram appear
DDR SDRAM Specific Parameters (DDR3/DDR3L and LPDDR2)
DDR3/DDR3L Parameters
DDR6
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
DDR4
Figure 24. DDR3/DDR3L Command and Address Timing Diagram
Parameter
ROW/BA
Table 43. DDR3/DDR3L Timing Parameter Table
DDR5
DDR5
DDR7
DDR4
DDR4
COL/BA
DDR5
Symbol
DDR4
t
t
CH
CL
DDR5
0.47
0.47
Min
DDR1
CK = 532 MHz
DDR2
Max
0.53
0.53
Freescale Semiconductor
Unit
t
t
CK
CK
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