MCIMX6S1AVM08ABR Freescale Semiconductor, MCIMX6S1AVM08ABR Datasheet - Page 134

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MCIMX6S1AVM08ABR

Manufacturer Part Number
MCIMX6S1AVM08ABR
Description
Processors - Application Specialized i.MX6 Solo rev 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX6S1AVM08ABR

Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Data Ram Size
16 KB
Operating Supply Voltage
1.175 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-624
Interface Type
Parallel
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
Electrical Characteristics
4.11.19.2 SSI Receiver Timing with Internal Clock
Figure 96
receiver timing with the internal clock.
134
SS11
SS13
SS20
SS21
SS1
SS2
SS3
SS4
SS5
SS7
SS9
ID
depicts the SSI receiver internal clock timing and
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
TXFS (wl)
(Output)
TXFS (bl)
(Output)
RGMII_TXC
(Output)
RGMII_RXC
(Output)
RGMII_RX
D
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Figure 96. SSI Receiver Internal Clock Timing Diagram
SS48
SS2
Table 88. SSI Receiver Timing with Internal Clock
SS7
Parameter
Oversampling Clock Operation
SS47
SS1
Internal Clock Operation
SS11
SS9
SS20
SS51
SS5
SS4
SS50
Table 88
SS21
lists the timing parameters for the
81.4
36.0
36.0
10.0
Min
0.0
SS49
SS3
Freescale Semiconductor
Max
15.0
15.0
15.0
15.0
6.0
6.0
SS13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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